Silicon Image, Inc. (408) ,

Transcription

1 fkldjlkadfoiejpdskdfkg;fdkl;fajg sdflkdaklsdflkl;fscdsfklfla dslfk;sldd;lfakgl;sdf;ls;daslgd sdlklflasd;lfdk;llsafk;ld sdlfldkfldfldk;las kdfldld; ;ds;ldf;;f ;d;lfkl ; ;dsff dsfldsf;lkldlkf;s;s dsf dflfsdklfk d;lfkl;f;ad;f fldflfdlkflkf dsklfkjlkf fklds lfkd;lk;fdsk;f Silicon Image, Inc. (408) , Introduction Moving into the 21 st century, digital flat panel displays (FPDs) will be ubiquitous, linked to everyday electronic appliances from desktop computers to DVD players to set-top boxes. By the turn of this century, we ll either own a digital FPD monitor, or know someone that does. Inevitably, as prices drop far enough, large screen, all-digital TVs will be the display of choice to maximize the all-digital video viewing experience. But to make all this happen, the consumer electronics and PC industry must adopt a digital interface standard to link digital video/graphics sources to digital FPDs. When the video is kept digital from source-to-fpd, the system is all-digital. CRT Analog Display FPD Digital Display CRT Statistics: 1995 Batting Avg:.327 RBIs: 115 HRs: 46 TV All-Digital Home Entertainment Notebook Automobile GPS Flat Panel Monitor This paper will first address the TMDS 1 interface standard and how it meets the FPD market requirements and then discuss PanelLink Digital by Silicon Image, Inc. ( the first off-the-shelf components that implement the TMDS standard. Requirements of an All-Digital FPD Interface Standard If FPDs are to expand into new and exciting multimedia/graphics applications and deliver the highest image quality possible, an all-digital FPD interface standard needs to exist. This all-digital FPD interface standard needs to be flexible, easy to use, cost effective while driving signals over long distances and transmitting data over various media types. Most important, it needs to maintain the same interface for any panel resolution, color depth or panel technology. An all-digital FPD interface must meet the following market requirements: scale to maintain the same interface, provide a low bit error rate for high image quality, transmit over standard twisted pair cables to keep connection cost low, support fiber optics to transmit video over extremely long distances, become a standard for widespread adoption in the electronics and PC industry, and ensures compatibility so that system and display products from different suppliers can be made available in an open market. VESA s 2 TMDS interface standard meets the FPD Market Criteria The TMDS digital-only video interface uses a coding scheme that was invented and developed by Silicon Image, Inc. and adopted by VESA. The TMDS digital-only video interface was designed with the goal of achieving high-speed digital video transmission over a scaleable, logical interface to support a wide range of FPDs. Moreover, the interface was developed to support various cable media types, such as fiber optics and low cost twisted pair, and to enable new FPD applications over long distances. Figure 1 shows a high-level diagram of the TMDS architecture. 1 Transition Minimized Differential Signaling 2 VESA is a standards organization comprised of leading PC, FPD, cable/connector and IC manufacturers 1

2 TMDS Transmitter High Speed Serializers TMDS Receiver Video/Graphics Controller TMDS TM Encoder Red Green Blue Red Green Blue TMDS TM Decoder Flat Panel Display Figure 1. VESA TMDS Architecture Diagram Silicon Image, Inc. Implements TMDS Architecture in PanelLink Digital PanelLink Digital incorporates the TMDS coding scheme and adds an associated physical layer to transmit pixel data, clock, and control signals serially at high speeds from the host system to the FPD, enabling an all-digital system. PanelLink Digital has three high-speed serial data channels and one clock channel to support the mainstream FPD resolutions (from VGA to UXGA) and prevalent FPD technologies (AMLCD, DSTN or Plasma). See Figure 2 below. Data Capture Logic TMDS DC-Balanced Encoder Serializer 3x Over- DPLL Sampler Deserializer Inter- Phase Byte Channel Sync High Speed SyncSampling Sync Decoder Flat Panel Graphics/ Video Controller Data 24/48 DE Controls (5) Channel 2 Channel 1 Channel 0 PLL Voltage Swing Control RED GREEN BLUE CLK PanelLink Transmitter Low Voltage Differential Signals 3 Data Pairs 1 CLK Pair Reflection Minimizer RED GREEN BLUE CLK Channel 2 Channel 1 Channel 0 PLL PanelLink Receiver Sync Detect Output Panel Interface Logic 640x x1024 SCDT (1600x1200) TFT and DSTN Data 24/48 DE Controls (5) Panel Control ASIC Figure 2. PanelLink Digital Block Diagram PanelLink Digital provides high quality data recovery, high skew tolerance, high-speed transmission over few wires, fiber optics support, interoperability, scaleability from VGA to UXGA and beyond, and compatibility. In addition, PanelLink Digital incorporates a patent-pending jitter filter that ensures crisp, stable displays even in the presence of extreme jitter across clock speeds needed to support up to UXGA. PanelLink Digital can input and output up to 24-bits of data for true color (16.7 million) support along with control signals, Display Enable,, Horizontal Synchronization, Vertical Synchronization, and up to three general purpose signals. PanelLink Digital can also detect if data transmission has been disconnected and provide a signal to safeguard the panel from damage. These features will each be described in further detail hereafter. Received Frequency Used for High Quality Data Recovery Precise, high-speed sampling of the received serial pixel data enables reliable data reception in the presence of noise. PanelLink Digital uses only the frequency, not the phase information to generate the data sampling clocks. This in turn provides clock-to-data skew immunity which helps keep the bit error rate extremely low. Figure 3 demonstrates data sampling of a single bit stream in one color channel. Note that the bit sampling is clock edge independent. Previous Transmit PanelLink Current Transmit Previous Cycle Current Cycle Previous 30x Multi-Phase Sampling s Independent Sampling points Current 30x Multi-Phase Sampling s Figure 3. High Speed Sampling and Skew Tolerant Diagram 2

3 Multi-Channel Synchronization for High Skew Tolerance PanelLink Digital employs Multi-channel synchronization to minimize the effects of cable skew that arises from the inherent differences in the wire lengths, composition, and impedance between each channel (channel-to-channel skew). Consequently, PanelLink Digital has extremely high skew tolerance as a result (see Figure 4). XGA T ck = 15.4ns Encoded RED bits Encoded GREEN bits Encoded BLUE bits Figure 4. Multi-Channel Skew Tolerance Again, the clock is used as a reference frequency, not as a means to latch in the data. Instead, PanelLink Digital uses an encoding scheme that allows up to a 1-input clock cycle channel-to-channel skew. The output circuits of the decoder then re-sync the data channels. This translates into 15.4nsec skew for XGA FPDs and 9.3nsec for SXGA FPDs, whereas only 100 to 250ps of skew tolerance is possible with other technologies that do not use encoding. Current Drive Enables High Speed Serial Transmission over Few Wires Low swing differential signaling eases the design for EMI compliance and enables reliable data transmission at very high speeds over few wires. As seen in Figure 5, the sum of the two output currents is constant, I S ; therefore, the only common mode signal is DC. At any given time, one switch is ON and the other is OFF, allowing the peak current of Is to flow through the on switch. Hence, the peak current drawn from the supply, which is equal to Is, is always constant (DC). Keeping Is constant, the current is steered alternately from one switch to the other, creating the differential signal. As a bit is transmitted over the high-speed differential wire pairs, the receiver reads the AC differential signal, eye opening, as a 1 or 0. /2) + (I+) /2) + (I-) I S /2) + (I+) +I D Data Data I S /2 I S 0 /2) + (I-) -I D Figure 5. Current Driving Method DC Balancing for Data Transmission over Fiber Optics In addition to providing high skew tolerance, PanelLink Digital s encoding scheme DC balances data. To directly interface to fiber optic transceivers, DC balancing is required. To date, PanelLink Digital has been able to transmit pixel data over 500 meters of fiber optic cable. Fiber optic video transmission opens up a wide variety of new applications and possibilities for multimedia and FPDs. VESA P&D Data Mapping Standard Overcomes Interoperability Problems Since each manufacturer of multimedia video/graphics accelerators such as ATI, Chips and Technologies, S3, and Trident, offers different output data mapping, there is a the need for a standard data mapping scheme for system designers. PanelLink Digital implements the standard data mapping scheme developed and endorsed by VESA. Table 1 shows the data-mapping scheme for the VESA P&D standard. In these data mapping schemes, the transmitter input is exactly the same as the receiver parallel output for color TFT and DSTN FPDs. The parallel input and the parallel output in turn match to the three-serial channels of the PanelLink Digital. In this way, the data-mapping scheme enables true interoperability between various FPDs types. 3

4 Transmitter Input Transmission Receiver Output TFT DSTN TFT DSTN TFT DSTN 24-bpp 18-bpp 24-bit 16-bit 24-bpp 18-bpp 24-bit 16-bit 24-bpp 18-bpp 24-bit 16-bit R7 R5 LB3 R7 R5 LB3 R6 R4 LG3 R6 R4 LG3 R5 R3 LR3 R5 R3 LR3 R4 R2 UB3 Serial Channel 3 R4 R2 UB3 R3 R1 UG3 R3 R1 UG3 R2 R0 UR3 R2 R0 UR3 R1 LB2 R1 LB2 R0 LG2 SCLK R0 LG2 SCLK G7 G5 LR2 LG2 G7 G5 LR2 LG2 G6 G4 UB2 LR2 G6 G4 UB2 LR2 G5 G3 UG2 LB1 G5 G3 UG2 LB1 G4 G2 UR2 LG1 Serial Channel 2 G4 G2 UR2 LG1 G3 G1 LB1 UG2 G3 G1 LB1 UG2 G2 G0 LG1 UR2 G2 G0 LG1 UR2 G1 LR1 UB1 G1 LR1 UB1 G0 UB1 UG1 G0 UB1 UG1 B7 B5 UG1 LR1 B7 B5 UG1 LR1 B6 B4 UR1 LB0 B6 B4 UR1 LB0 B5 B3 LB0 LG0 B5 B3 LB0 LG0 B4 B2 LG0 LR0 Serial Channel 1 B4 B2 LG0 LR0 B3 B1 LR0 UR1 B3 B1 LR0 UR1 B2 B0 UB0 UB0 B2 B0 UB0 UB0 B1 UG0 UG0 B1 UG0 UG0 B0 UR0 UR0 B0 UR0 UR0 Table 1. VESA P&D Data Mappings for Color 24-bpp and 18-bpp 1-pixel/clock TFT and 24-bit and 16-bit DSTN FPD Support 3,4 Note: For 1-pixel/clock TFT FPDs, the above data mapping scheme transmits RED data on serial data channel 3, GREEN data on serial data channel 2, and BLUE data on serial data channel 1. This is the same methodology as an analog RGB interface, where data is transmitted over three individual channels to the CRT monitor, and hence, the same logical data mapping scheme already familiar to the market. PanelLink Digital Scales to Support Same Interface from VGA to UXGA Resolutions An 8-bit-per-pixel (bpp) VGA (640 x 480) flat panel at a 60Hz refresh rate required only a 25MHz pixel clock speed. Today, a clock speed of 108MHz is required to support 24-bpp SXGA (1280x1024) flat panels at 60Hz refresh. In the near future, the market will demand clock speeds of greater than 135MHz for UXGA. Table 2 shows the clock speeds required for various resolutions for the associated VESA compatible normal CRT (normal blanking) and Generalized Timing Format (GTF TM ) (reduced blanking) refresh rates. Normal CRT Timing GTF Timing Resolution 60Hz 75Hz 60Hz 75Hz 640 x 480 (VGA) 25MHz 31.5MHz 19MHz 24MHz 800 x 600 (SVGA) 40MHz 49.5MHz 30MHz 37MHz 1024 x 768 (XGA) 65MHz 78.75MHz 48MHz 60MHz 1280 x 1024 (SXGA) 108MHz 135MHz 81MHz 101MHz 1600 x 1200 (UXGA) 162MHz 202.5MHz 120MHz 149MHz Table 2. Speeds for Various Resolutions for VESA Compatible Rates 1,2 To support the respective clock frequencies in Table 2, a single, scaleable, standard digital interface is required, such as PanelLink Digital. Without scaleability, the number of color channels in a data transmission interface would have to increase continuously, constantly requiring a new interconnect solution. Table 3 not only demonstrates that PanelLink 4

5 Digital scales to support the various clock frequencies, but also that it provides the required bandwidth to take care of the corresponding panel data rate requirements. Normal CRT Timings GTF Timings Resolution VGA SVGA XGA SXGA UXGA VGA SVGA XGA SXGA UXGA Speed (MHz) Data Transmit (Mbits/sec) Total Throughput (Mbits/sec) # of Chips One Constant Interface (1 Transmitter, 1 Receiver) # of Serial Channels 3 Data Channels and 1 Channel Table 3. Performance Scaling for PanelLink Digital for 60Hz PanelLink Digital Product Family Supports Compatibility Cross-compatibility for an FPD interface standard means that a PanelLink Digital transmitter in the host system must be compatible with a PanelLink Digital receiver in the FPD. Figure 6 below shows the compatibility of various PanelLink Digital transmitters (SiI 100, SiI 140 and SiI 150) with PanelLink receivers (SiI 101, SiI 141, and SiI 151) over the same interface supporting multiple panel resolutions. Cross compatibility is a key requirement because it will encourage the adoption of digital-out as a standard feature for desktop and notebook computers, and consumer electronic products. This, as a result, greatly accelerates the adoption rate of FPD monitors and new applications for FPDs. Panel Resolutions Supported SiI 100 transmitter SiI 101 receiver VGA to XGA SiI 140 transmitter SiI 141 receiver VGA to high refresh rate XGA SiI 150 transmitter SiI 151 receiver SXGA Figure 6. Compatibility Table of PanelLink Digital PanelLink Digital components will be available in the future to support UXGA panels. All-Digital FPD Applications Enabled by PanelLink Digital 1. High FPDs 2. Notebook computers 3. Flat Panel Projectors 4. TVs/Home Entertainment Systems 5. SetTop Boxes 6. Kiosks 7. Video Walls 8. GPS 9. NetPC, Network PC, WebBrowser 10. Embedded Control Systems 5

6 Conclusion PanelLink Digital implements the TMDS coding scheme from VESA to meet the PC and consumer electronics industry needs for an all-digital FPD interface that supports standard resolutions (VGA to UXGA and beyond) and various flat panel technologies (TFT, DSTN, and Plasma). PanelLink Digital allows multimedia system manufacturers to design FPD solutions with confidence knowing that the all-digital interface will remain constant across various technologies and performance requirements across product generations into the next century. The PanelLink Digital logo is supported by Silicon Image, Inc., the leading supplier of PanelLink Digital components for display, computer and consumer electronics manufacturers. Table 4 below summarizes key features and benefits of PanelLink Digital. PanelLink Features User Benefits Universal Transmitter MHz (VGA - SXGA) - Scaleable SiI150 Full Compatibility with various resolution receivers (SiI101, SiI141, and SiI151) One Constant Interface Advanced Jitter Filter Robust interface to multimedia controllers Circuitry Minimize effects of jitter Only Frequency (not -to-data Skew Tolerant Designs for long distance cable support Phase) Information Used Minimize effect of noise Precise Sampling of Data Reliable Data Recovery for long distance cable support Minimize effects of noise Multi-Channel Data-to-Data Skew Tolerant Designs (up to 1-input clock cycle) for long distance cable Synchronization support and to enable lower cost computer monitor cables Current Drive Symmetrical Data Transmission Minimizes Common mode noise DC-Balancing Direct Fiber Optic transceiver support Adjustable Voltage Swing Supports Various Lengths and Quality cables for special applications Adjustable Impedance Minimizes Transmission Line Reflections for Reliable Data Reception Matching 24/48-bit One/Two pixel/clock Support True Color (16.7 million) Support Supports various types of panels Sync Detect Provides panel power sequencing indication for panel longevity Hot-Plug support VESA TMDS Standard Plug and Display (P&D) for Flat Panel Monitors (FPD) Flat Panel Display Interface -2 (FPDI - 2 TM ) for Notebook Applications One Constant Interface Table 4. Summary of Features and Benefits of PanelLink Digital References : 1. VESA Monitor Timing Standard 2. VESA GTF Timing Standard 3. VESA P&D Standard 4. VESA FPDI-2 Standard Silicon Image, the Silicon Image Logo, PanelLink, and the PanelLink Digital Logo are trademarks of Silicon Image, Inc. All other trademarks are properties of their respective owners. 6