Two s Complement Arithmetic. Introduction to Combinational Logic Circuits. (Class 1.2 8/30/2012)

Transcription

1 Two s Complement Arithmetic. Introduction to Combinational Logic Circuits. (Class 1.2 8/30/2012) CSE 2441 Introduction to Digital Logic Fall 2012 Instructor Bill Carroll, Professor of CSE

2 Today s Topics Reminder check course website regularly Two s complement arithmetic Digital logic circuit taxonomy Basic logic gates AND, OR, NOT, NAND, NOR, XOR Truth tables, logic equations Half adders and full adders Basic Verilog statements and modules

3 Signed Binary Numbers (n=4) Decimal Sign-Magnitude Two s Complement One s Complement , , NA 1000 NA

4 Two s Complement Arithmetic (1) Two s complement number systems are used in computer systems since this reduces hardware requirements (only adders are needed). A - B = A + (-B) (add r s complement of B to A) Range of numbers in two s complement number system, where n is the number of bits. 2 n-1-1 = (0, ) 2cns and -2 n-1 = (1, ) 2cns If the result of an operation falls outside the range, an overflow condition is said to occur and the result is not valid. Consider three cases (where B 0 and C 0): A = B + C A = B - C A = - B - C

5 Two s Complement Arithmetic (2) Case 1: A = B + C (A) 2 = (B) 2 + (C) 2 If A > 2 n-1-1 (overflow), it is detected by a sign bit = 1 in A. Example: (7) 10 + (4) 10 =? using 4-bit two s complement arithmetic. + (5) 10 = +(101) 2 = (0101) 2cns + (2) 10 = +(010) 2 = (0010) 2cns (0101) 2cns + (0010) 2cns = (0111) 2cns = +(111) 2 = +(7) 10 No overflow. Example: (5) 10 + (6) 10 =? + (5) 10 = +(101) 2 = (0101) 2cns + (6) 10 = +(110) 2 = (0110) 2cns (0101) 2cns + (0110) 2cns = (1011) 2cns (overflow)

6 Two s Complement Arithmetic (3) Case 2: A = B - C A = (B) 2 + (-(C) 2 ) = (B) 2 + [C] 2 = (B) n - (C) 2 = 2 n + (B - C) 2 If B C, then A 2 n and the carry is discarded. So, (A) 2 = (B) 2 + [C] carry discarded If B < C, then A = 2 n - (C - B) 2 = [C - B] 2 or A = -(C - B) 2 (no carry in this case). No overflow for Case 2. Example: (7) 10 - (3) 10 =? Perform (7) 10 + (-(3) 10 ) (7) 10 = +(0111) 2 = (0111) 2cns -(3) 10 = -(0011) 2 = (1101) 2cns (7) 10 - (3) 10 = (0111) 2cns + (1101) 2cns = (0100) 2cns + carry = +(0100) 2 = +(4) 10

7 Two s Complement Arithmetic (4) Example: (3) 10 - (7) 10 =? Perform (3) 10 + (-(7) 10 ) (3) 10 = +(011) 2 = (0011) 2cns -(7) 10 = -(111) 2 = (1001) 2cns (3) 10 - (7) 10 = (0011) 2cns + (1001) 2cns = (1100) 2cns = -(0100) 2 = -(4) 10

8 Two s Complement Arithmetic (5) Case 3: A = -B - C A = [B] 2 + [C] 2 = 2 n - (B) n - (C) 2 = 2 n + 2 n - (B + C) 2 = 2 n + [B + C] 2 The carry bit (2 n ) is discarded. An overflow can occur, in which case the sign bit is 0. Example: -(5) 10 - (2) 10 =? Perform (-(5) 10 ) + (-(2) 10 ) -(5) 10 = -(0101) 2 = (1011) 2cns, -(2) 10 = -(0010) 2 = (1110) 2cns -(5) 10 - (2) 10 = (1011) 2cns + (1110) 2cns = (1001) 2cns + carry = -(0111) 2 = -(7) 10 Example: -(5) 10 - (7) 10 =? Perform (-(5) 10 ) + (-(7) 10 ) -(5) 10 = (1011) 2cns, -(7) 10 = -(0111) 2 = (1001) 2cns -(5) 10 - (7) 10 = (1011) 2cns + (1001) 2cns = (0100) 2cns + carry Overflow, because the sign bit of the result is 0.

9 Two s Complement Arithmetic (6) Example: A = (25) 10 and B = -(46) 10, n = 8 A = +(25) 10 = ( ) 2cns, -A = ( ) 2cns B = -(46) 10 = -( ) 2 = ( ) 2cns, -B = ( ) 2cns A + B = ( ) 2cns + ( ) 2cns = ( ) 2cns = -(21) 10 A - B = A + (-B) = ( ) 2cns + ( ) 2cns = ( ) 2cns = +(71) 10 B - A = B + (-A) = ( ) 2cns + ( ) 2cns = ( ) 2cns + carry = -( ) 2cns = -(71) 10 -A - B = (-A) + (-B) = ( ) 2cns + ( ) 2cns = (0, ) 2cns + carry = +(21) 10

10 Two s Complement Arithmetic (7) Summary Case Carry Sign Bit Condition Overflow? B + C B + C 2 n-1-1 B + C > 2 n-1-1 No Yes B - C B C B > C No No -B - C (B + C) -2 n-1 -(B + C) < -2 n-1 No Yes When numbers are represented using 2 s complement number system: Addition: Add two numbers. Subtraction: Add two s complement of the subtrahend to the minuend. Carry bit is discarded, and overflow is detected as shown above.

11 Digital Logic Circuit Taxonomy Combinational Circuits Primary characteristic -- memoryless Primary building blocks -- logic gates Sequential circuits Primary characteristic -- memory Primary building blocks -- logic gates, flip-flops Types Synchronous (clocked) Asynchronous (unclocked)

12 Combinational Logic Circuits and Truth Tables Block Diagram Circuit Diagram j k l Truth Table a b c z Logic Equation z = ab + ac + bc Verilog HDL Code module LogicCircuit (a,b,c,z); input a,b,c; output z; wire j,k,l; and (j,a,b); and (k,b,c); and (l,a,c); or (z,j,k,l); endmodule

13 Basic Logic Gates AND, OR, NOT AND gate OR Gate NOT Gate a b f a b f a f a b f f = a b and(f,a,b) a b f f = a + b or(f,a,b) a f f = a not(f,a)

14 Basic Logic Gates NAND, NOR NAND gate NOR gate a b f a b f a b f f = (a b) nand(f,a,b) a b f f = (a + b) nor(f,a,b)

15 Exclusive-OR (XOR) a b f b ab a a b f = a b f = ab + a b xor(f,a,b)

16 Test Your Understanding XOR3 gate Logic equation f =? Verilog code a b c f

17 Test Your Understanding Self-Check XOR3 gate Logic equation f =? f = a b c Verilog code xor(f,a,b,c) a b c f

18 XOR3 Realizations g = f c = (a b) c = a b c = a b c + a bc + ab c + abc

19 Half Adder Output logic equations s = a b cout = a b a b cout s

20 Full Adder Realization Output logic equations s = a b cin = a b cin + a bcin + ab cin + abc cout = a bcin + ab cin + abcin + abcin = ab + acin + bcin = majority (a,b,cin) Logic Circuit Diagram

21 FA = HA + HA + OR2

22 HA and FA Verilog Code module halfadder (s, cout, a, b); input a, b; output s, cout; and (cout, a, b); xor (s, a, b); endmodule module fulladder (s, cout, a, b, cin); input a, b, cin; output s, cout; wire d, e, f, g; xor (d, a, b); xor (s, d, cin); and (e, a, b); and (f, a, cin); and (g, b, cin); or (cout, e, f, g); endmodule

23 Summary of Basic Logic Gates

24 Dual In-line Packages (DIP) 1 Vcc 4B 4A 4Y 3B 3A 3Y Vcc 4Y 4B 4A 3Y 3B 3A Power signals 4.75 Vcc 5.25 volts GND = 0 volts A 1B 1Y 2A 2B 6 2Y 7 GND 7400: Y = AB Quadruple two-input NAND gates Y 1A 1B 2Y 2A 6 2B 7 GND 7402: Y = A + B Quadruple two-input NOR gates Inputs signals 0 L 0.8 volts 2.0 H 5.25 volts Vcc 6A 6Y 5A 5Y 4A 4Y Vcc 4B 4A 4Y 3B 3A 3Y A 1Y 2A 2Y 3A 7404: Y = A Hex inverters 6 3Y 7 GND A 1B 1Y 2A 2B 6 2Y 7408: Y = AB Quadruple two-input AND gates 7 GND Chapter 2 24

25 Dual In-line Packages (DIP) 2 Vcc 1C 1Y 3C 3B 3A 3Y Vcc 2D 2C NC 2B 2A 2Y A 1B 2A 2B 2C Y 7410: Y = ABC Triple three-input NAND gates 7 GND A 1B NC 1C 1D Y 7420: Y = ABCD Dual four-input NAND gates 7 GND Chapter 2 25

26 Dual In-line Packages (DIP) 3 Vcc NC H G NC NC Y Vcc 4B 4A 4Y 3B 3A 3Y A B C D E : Y = ABCDEFGH 8-input NAND gate 6 F 7 GND A 1B 1Y 2A 2B Y 7432: Y = A + B Quadruple two-input OR gates 7 GND Vcc 4B 4A 4Y 3B 3A 3Y A 1B 1Y 2A 2B Y 7 GND 7486: Y = A Å B Quadruple two-input exclusive-or gates Chapter 2 26

27 Positive and Negative Logic Electrical Signals and Logic Values Electric Signal Logic Value Positive Logic Negative Logic High Voltage (H) 1 0 Low Voltage (L) 0 1 A signal that is set to logic 1 is said to be asserted, active, or true. An active-high signal is asserted when it is high (positive logic). An active-low signal is asserted when it is low (negative logic). For TTL devices, 0 L 0.8 volts, 2 H 5.25 Volts Chapter 2 27