Analysis and Design of Analog Integrated Circuits Lecture 23. Analog to Digital Conversion

Transcription

1 Analysis and Design of Analog Integrated Circuits Lecture 23 Analog to Digital Conversion Michael H. Perrott April 25, 2012 Copyright 2012 by Michael H. Perrott All rights reserved.

2 Outline of Lecture ADC Topologies - Flash - SAR - Pipeline - Interleaved - Sigma-Delta Special focus on the emerging area of VCO-based ADCs 2

3 Analog to Digital Conversion D 2 D 1 D V in ADC D 0 D 1 D N V ref 1 LSB 7 8 V ref V in Analog input is typically voltage Digital output consists of bits, D k, with values 0 or 1 Key characteristics similar to DAC - Full scale = V ref - Resolution = V ref /2 N = 1 LSB - Nonlinearity measured with INL, DNL, Monotonicity 3

4 Flash ADC N-Stage Resistor Ladder Pre-Amp A Comparator 0 Vref N A A 1 1 IN CLK Fastest ADC structure (> 1 GHz) - Performs direct comparison of an input signal to a set of voltage references using parallel comparators - Typically limited to 8-bit resolution - Relatively large area and power for higher resolution 4

5 SAR ADC V ref D N-1 D N-2 D 2 D 1 D 0 D 0 D 1 DAC V dac 2 N-1 C 2 N-2 C 4C 2C C Φ 0 D N-1 V in CLK V dac C Leverages a DAC to sequentially compare its output values to the input voltage - Minimal analog complexity - requires only one comparator and a capacitor DAC - Successive Approximation Algorithm (SAR) is efficient comparison algorithm for comparing DAC to input value - Has recently become very attractive in advanced CMOS V in CLK for modest resolution (i.e., 8 to 10 bits) applications 5

6 SAR Algorithm V ref V in Gnd D5 =0 D 4 =1 D 3 =1 D 2 =0 D 1 =0 D 0 =0 We can efficiently compare the DAC output to the input voltage, V in, by successively subdividing the range from MSB to LSB - Number of comparisons number of bits Example: 10-bit SAR ADC requires roughly 10 comparisons per sample 6

7 Pipeline ADC V in K V residue1 K V residue2 ADC D 0 DAC V dac1 ADC D 0 DAC V dac2 D J-1 D J-1 CLK Resolves ADC bits in several stages - Earlier stages resolve MSB bits - Calculate residue for later stages through subtraction of MSB estimate Amplify residue so that all stages operate over similar voltage ranges Pipeline trends - 1-bit per stage in the past; now going to multi-bit per stage - For advanced CMOS, interleaved SAR architectures are starting to look more attractive than pipelines 7

8 Interleaved ADC D 0 V D in 1 CLK1 CLK2 CLK3 CLK4 ADC ADC ADC ADC D N-1 D 0 D 1 D N-1 D 0 D 1 D N-1 D 0 D 1 D N-1 CLK1 CLK2 CLK3 CLK4 Clocking several ADC structures at different clock phases allows much higher effective sample rate - Can interleave Flash, SAR, or Pipeline ADCs Key challenges include clock skew, mismatch between ADCs, higher input capacitance 8

9 Sigma-Delta ADC (Discrete-Time) IN H(z) Multi-Level Quantizer OUT clock DAC Oversampled input - Clock rate is much higher than bandwidth of input signal Noise shaped quantization noise - Uses similar concepts as Sigma-Delta DAC considered in Lecture 22 Leads to high effective precision despite having a coarse quantizer 9

10 Sigma-Delta ADC (Continuous-Time) IN H(s) Multi-Level Quantizer OUT DAC clock Similar to Discrete-Time, but important differences - Sampler occurs after the filtering Allows removal of high frequency noise before sampling - Only the quantizer and DAC need to settle during each sample Allows higher speed 10

11 Time-to-Digital Conversion tin(t) Delay Delay Delay clk(t) e[k] tin(t) clk(t) Delay Δt e[k] tin(t) Time -to- Digital clk(t) TDC Characteristic Quantization in time achieved with purely digital gates - Easy implementation, resolution improving with Moore s law e[k] e[k] Δt How can we leverage this for quantizing an analog voltage? 11

12 Adding Voltage-to-Time Conversion in(t) Voltage -to- Time tin(t) Time -to- Digital out[k] Naraghi, Courcy, Flynn, ISSCC 2009 clk(t) Analog voltage is converted into edge times - Time-to-digital converter then turns the edge times into digitized values Key issues - Non-uniform sampling - Noise, nonlinearity Is there a simple implementation for the Voltage-to-Time Converter? 12

13 A Highly Digital ADC Implementation in(t) Ring Oscillator (t) tin(t) tin(t) Delay Delay Delay clk(t) out[k] in(t) Voltage -to- Time tin(t) Time -to- Digital out[k] clk(t) A voltage-controlled ring oscillator offers a simple voltage-to-time structure - Non-uniform sampling is still an issue We can further simplify this implementation and lower the impact of non-uniform sampling 13

14 Making Use of the Ring Oscillator Delay Cells in(t) Ring Oscillator (t) tin(t) tin(t) Delay Delay Delay clk(t) out[k] in(t) Ring Oscillator (t) tin 1 (t) tin 2 (t) tin 3 (t) tin 3 (t) tin 2 (t) tin 1 (t) clk(t) out[k] Utilize all ring oscillator outputs and remove TDC delays - Simpler implementation TDC output now samples/quantizes phase state of oscillator 14

15 Improving Non-Uniform Sampling Behavior in(t) Ring Oscillator (t) tin(t) tin(t) Delay Delay Delay clk(t) out[k] in(t) Ring Oscillator (t) tin 1 (t) tin 2 (t) tin 3 (t) tin 3 (t) tin 2 (t) tin 1 (t) clk(t) out[k] Oscillator edges correspond to a sample window of the input Sampling the oscillator phase state yields sample windows that are much more closely aligned to the TDC clk 15

16 Multi-Phase Ring Oscillator Based Quantizer N-Stage Ring Oscillator N-Stage Ring Oscillator Ref N-bit ister Sample 1 N-bit ister N XOR Gates Sample 2 Adder Out Sample 3 Adjustment of changes how many delay cells are visited by edges per Ref clock period Sample 4 - Quantizer output corresponds to the number of delay cells that experience a transition in a given Ref clock period 16

17 More Details N-Stage Ring Oscillator Example: Progression of 9-Stage Ring Oscillator Values Ref N-bit ister Ref N-bit ister N XOR Gates Adder Choose large enough number of stages, N, such that transitions never cycle through a given stage more than once per Ref clock period - Assume a high Ref clock frequency (i.e., 1 GHz) XOR operation on current and previous samples provides transition count Out Out = 4 Out = 6 Out = 5 17

18 A First Step Toward Modeling Ref N-Stage Ring Oscillator N-bit ister Quantized VCO Phase Sampler VCO Ref Quantizer First Order Difference Out 1- z -1 N-bit ister T Wismar, Wisland, Andreani, ESSCIRC 2006 N XOR Gates Adder First Order Difference Out Quantized VCO Frequency Out = 6 Out = 5 VCO provides quantization, register provides sampling - Model as separate blocks for convenience XOR operation on current and previous samples corresponds to a first order difference operation - Extracts VCO frequency from the sampled VCO phase signal 18

19 Corresponding Frequency Domain Model VCO modeled as integrator and K v nonlinearity Sampling of VCO phase modeled as scale factor of 1/T Quantizer modeled as addition of quantization noise VCO T Ref Quantizer First Order Difference Out 1- z -1 Key non-idealities: - VCO K v nonlinearity - VCO noise - Quantization noise VCO Noise -20 db/dec Quantization Noise Output Noise 20 db/dec f f f 2πK v s 1 T 1- z -1 Out VCO K v Nonlinearity VCO Sampler First Order Difference 19

20 Example Design Point for Illustration Amplitude (db) Simulated ADC Output Spectrum Ref clk: 1/T = 1 GHz 31 stage ring oscillator - Nominal delay per stage: 65 ps K VCO = 500 MHz/V - 5% linearity VCO noise: -100 dbc/hz at 10 MHz offset Frequency (Hz) VCO Noise -20 db/dec f Quantization Noise f Output Noise 20 db/dec f 2πK v s 1 T 1- z -1 Out VCO K v Nonlinearity VCO Sampler First Order Difference 20

21 SNR/SNDR Calculations with 20 MHz Bandwidth 60 Simulated ADC Output Spectrum Conditions SNDR Amplitude (db) Ideal VCO Thermal Noise VCO Thermal + Nonlinearity 68.2 db 65.4 db 32.2 db Frequency (Hz) VCO K v nonlinearity is the key performance bottleneck VCO K v Nonlinearity 2πK v s VCO VCO Noise -20 db/dec f 1 T Sampler Quantization Noise f 1- z -1 First Order Difference Output Noise 20 db/dec Out f 21

22 Classical Analog Versus VCO-based Quantization N-Stage Resistor Ladder Pre-Amp Comparator IN N-Stage Ring Oscillator A 0 Vdd Vdd N A A 1 1 CLK Buffer N-bit ister IN CLK Much more digital implementation Offset and mismatch is not of critical concern Metastability behavior is potentially improved Improved SNR due to quantization noise shaping Implementation is high speed, low power, low area 22

23 Key Performance Issues: Nonlinearity and Noise Very hard to build a simple ring oscillator with linear K v Noise floor set by VCO phase noise is typically higher than for analog amplifiers at same power dissipation Ref N-Stage Ring Oscillator N-bit ister N-bit ister N XOR Gates Adder Out 20 db/dec Quantization Noise VCO Noise f Out VCO K v Nonlinearity 23

24 Feedback Is Our Friend In Gain and Filtering VCO-based Quantizer Ref (1 GHz) Out Iwata, Sakimura, TCAS II, 1999 Naiknaware, Tang, Fiez, TCAS II, 2000 N-Stage Ring Oscillator DAC Out DAC Combining feedback with front end gain acts to suppress impact of quantizer noise and nonlinearity - Scale factor from input to output is also better controlled - Structure is a continuous-time Sigma-Delta ADC Ref N-bit ister N-bit ister N XOR Gates Adder Issue: must achieve a highly linear DAC structure - Otherwise, noise folding and other bad things happen Out 24

25 A Closer Look at the DAC Implementation Ref (1 GHz) In Gain and Filtering VCO-based Quantizer Out N-Stage Ring Oscillator DAC Out DAC Ref N-bit ister Consider direct connection of the quantizer output to a series of 1-bit DACs - Add the DAC outputs together What is so special about doing this? N-bit ister N XOR Gates 1-Bit DACs DAC Out 25

26 Recall that Ring Oscillator Offers Implicit Barrel Shifting Ref (1 GHz) In Gain and Filtering VCO-based Quantizer Out N-Stage Ring Oscillator DAC Out DAC Sample 1 Barrel shifting through delay elements - Mismatch between delay elements is first order shaped Sample 2 Sample 3 Sample 4 26

27 Implicit Barrel Shifting Applied to DAC Elements Ref (1 GHz) Miller, US Patent (2004) In Gain and Filtering VCO-based Quantizer Out N-Stage Ring Oscillator DAC Out DAC Implicit Barrel-Shift DEM Ref N-bit ister N-bit ister Ref Barrel shifting action of quantizer transferred to 1-bit DAC elements N XOR Gates 1-Bit DACs DAC Out - Acts to shape DAC mismatch and linearize its behavior 27

28 First Generation Prototype 973 MHz V IN I DAC1 V A V B VCO-based Quantizer & Barrel-Shift DEM I DAC2 31 D OUT Quantizer Element Barrel-Shift DEM Second order dynamics achieved with only one op-amp - Op-amp forms one integrator - I dac1 and passive network form the other (lossy) integrator - Minor loop feedback compensates delay through quantizer Third order noise shaping is achieved! Sample - VCO-based quantizer adds an extra order of noise shaping 28

29 Custom IC Implementing the Prototype V IN 973 MHz V A V B VCO-based Quantizer & Barrel-Shift DEM D OUT Straayer, Perrott VLSI 2007 I DAC1 I DAC u CMOS Power: 40 mw Active area: 700u X 700u Peak SNDR: 67 db (20 MHz BW) Efficiency: 0.5 pj/conv. step 29

30 Measured Spectrum From Prototype Amplitude (db) Normalized FFT, F IN = 1 MHz Distortion 20 MHz Input Bandwidth SNR 66.4 db SNDR 65.7 db Frequency (MHz) 30

31 Measured SNR/SNDR Vs. Input Amplitude (20 MHz BW) 90 SNR/SNDR vs. Amplitude, F IN = 1 MHz SNR/SNDR (db) SNR SNDR K v nonlinearity limits SNDR to 67 db Amplitude (dbfs) 31

32 Summary ADC design is an active area of research - Many topologies possible - Much innovation is still ongoing, especially as new CMOS fabrication processes are introduced Key topologies - Flash - SAR - Pipeline - Sigma-Delta VCO-based ADCs are a new area of interest - Take advantage of high speed of new CMOS processes - Leverage digital circuits - Can achieve good performance, but innovation still needed 32