Analysis and Design of Analog Integrated Circuits Lecture 22. Digital to Analog Conversion

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1 Analysis and Design of Analog Integrated Circuits Lecture 22 Digital to Analog Conversion Michael H. Perrott April 22, 2012 Copyright 2012 by Michael H. Perrott All rights reserved.

2 Outline of Lecture Basic DAC Specifications Types of DACs (Resistive, Current, Capacitive) Impact of dynamic operation (NRZ, RZ) Sigma-Delta operation for high resolution 2

3 Digital to Analog Conversion D 0 D 1 D N-1 DAC V out or I out V out 1 LSB Digital input consists of bits, D k, with values 0 or 1 Analog output is either voltage or current Key characteristics - Full scale = D 2 D 1 D 0 V out = 2 N (2N 1 D N 1 +2 N 2 D N D D 0 ) - Resolution = /2 N = 1 LSB 3

4 Gain and Offset Errors V out Offset Error V out Gain Error V offset D 2 D 1 D D 2 D 1 D 0 Offset is most easily characterized as V offset = V out Dk =0 Gain error is characterized either as - Error at full scale (in LSBs) - Percentage of full scale 4

5 Nonlinearity 7 8 V out Nonlinearity INL D 2 D 1 D 0 Integral Non-Linearity (INL) - Maximum deviation from the ideal line characterisitic Typically specified in units of LSBs Differential Non-Linearity (DNL) - Maximum deviation of all codes from their ideal step size of 1 LSB 5

6 Monotonicity V out Non-Monotonic D 2 D 1 D 0 Monotonic behavior requires that stepping any code to the next code yields a step in the output that is always the same sign - Important in systems which utilize the D/A converter as part of a feedback Non-monotonicity yields changes in the sign of the gain, which can lead to small signal stability problems 6

7 Binary Resistor DAC D 2 D 1 2R 4R 8R D 0 Gnd R V out C L Relies on accurate resistor ratios for good INL/DNL Issues - Switches contribute resistance Can impact accuracy without clever design measures - Resistors require significant area for a high resolution DAC 7

8 Binary Current DAC 4I ref 2I ref I ref D 2 D 1 D 0 R V out C L Advantages - Switch resistance does not impact accuracy (to first order) - Scaled current sources are readily obtained using current mirror techniques Issues - Likely to have higher 1/f noise than resistor based DAC - Opamp limits bandwidth, adds noise 8

9 Binary Current DAC with Resistive Load 4I ref 2I ref I ref D 2 D 1 D 0 V out R C L No opamp required - Useful for high speed applications Issues - Current sources must now bear the full output range Much harder to maintain constant current from them Cascoding takes up headroom Can lead to code dependent nonlinearity (i.e., poor INL, distortion) 9

10 Binary Versus Thermometer Encoding Binary Thermometer R V out D 2 D 1 2R 4R 8R D 0 Gnd R R C L V out C L R R Binary-to-Thermometer Decoder D 2 D 1 D 0 Thermometer encoded resistor ladder provides inherently monotonic behavior Issues for high resolution - Decoding becomes very complex - Area can be quite large 10

11 Capacitor DAC D N-1 D N-2 D 2 D 1 D 0 2 N-1 C 2 N-2 C 4C 2C C Φ 0 C V out Uses charge re-distribution on a capacitor network to realize output voltages - Key advantage is that capacitor matching is quite good in CMOS processes - Has become the preferred approach for low to modest speed discrete-time ADCs 11

12 Operational Details of Capacitor DAC D N-1 D N-2 D 2 D 1 D 0 2 N-1 C 2 N-2 C 4C 2C C Φ 0 C V out First discharge all capacitors to zero (D k = 0, 0 = 1) Set P 0 = 0 and then set D k values V out = 2 N C ³ DN 1 2 N 1 C + D N 2 2 N 2 C N D 1 2C + D 0 C V out = 2 N ³ DN 1 2 N 1 + D N 2 2 N D 1 2+D 0 12

13 Seeking Higher Resolution V out D 0 D 1 D N-1 DAC V out or I out 1 LSB D 2 D 1 D 0 Increasing the number of levels in the DAC achieves higher resolution at the cost of complexity and power - At some point, improved resolution becomes impractical with this approach An alternative approach is to consider dithering between levels of a coarse DAC - By averaging the output, we can obtain resolution finer than the LSB of the coarse DAC 13

14 Sigma-Delta Modulation Time Domain M-bit Input Digital Σ Δ Modulator 1-bit D/A Analog Output Digital Input Spectrum Quantization Noise Frequency Domain Analog Output Spectrum Input Σ Δ Sigma-Delta dithers in a manner such that resulting quantization noise is shaped to high frequencies 14

15 Linearized Model of Sigma-Delta Modulator r[k] S r (e j2πft )= z=e j2πft STF q[k] x[k] y[k] x[k] y[k] H Σ Δ s (z) z=e j2πft Composed of two transfer functions relating input and noise to output - Signal transfer function (STF) Filters input (generally undesirable) - Noise transfer function (NTF) Filters (i.e., shapes) noise that is assumed to be white 15 NTF H n (z) S q (e j2πft )= H n (e j2πft )

16 Example: Cutler Sigma-Delta Topology x[k] u[k] y[k] H(z) - 1 e[k] Output is quantized in a multi-level fashion Error signal, e[k], represents the quantization error Filtered version of quantization error is fed back to input - H(z) is typically a highpass filter whose first tap value is 1 i.e., H(z) = 1 + a 1 z -1 + a 2 z -2 - H(z) 1 therefore has a first tap value of 0 Feedback needs to have delay to be realizable 16

17 Linearized Model of Cutler Topology x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Represent quantizer block as a summing junction in which r[k] represents quantization error - Note: It is assumed that r[k] has statistics similar to white noise - This is a key assumption for modeling often not true! 17

18 Calculation of Signal and Noise Transfer Functions x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Calculate using Z-transform of signals in linearized model - NTF: H n (z) = H(z) - STF: H s (z) = 1 18

19 A Common Choice for H(z) 8 7 m = 3 6 Magnitude m = 2 m = Frequency (Hz) 19 1/(2T)

20 Example: First Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 1 Amplitude Magnitude (db) 0 0 Sample Number Frequency (Hz) 1/(2T) 20

21 Example: Second Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 2 Amplitude 1 0 Magnitude (db) -1 0 Sample Number Frequency (Hz) 1/(2T) 21

22 Example: Third Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of Amplitude Sample Number Frequency (Hz) 1/(2T) 22 Magnitude (db)

23 Observations Low order Sigma-Delta modulators do not appear to produce shaped noise very well - Reason: low order feedback does not properly scramble relationship between input and quantization noise Quantization noise, r[k], fails to be white Higher order Sigma-Delta modulators provide much better noise shaping with fewer spurs - Reason: higher order feedback filter provides a much more complex interaction between input and quantization noise 23

24 Warning: Higher Order Modulators May Still Have Tones Quantization noise, r[k], is best whitened when a sufficiently exciting input is applied to the modulator - Varying input and high order helps to scramble interaction between input and quantization noise Worst input for tone generation are DC signals that are rational with a low valued denominator - Examples (third order modulator with no dithering): x[k] = 0.1 x[k] = /1024 Magnitude (db) Magnitude (db) 0 Frequency (Hz) 1/(2T) 0 Frequency (Hz) 1/(2T) 24

25 Fractional Spurs Can Be Theoretically Eliminated See: - M. Kozak, I. Kale, Rigorous Analysis of Delta-Sigma Modulators for Fractional-N PLL Frequency Synthesis, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 51, no. 6, pp S. Pamarti, I. Galton, "LSB Dithering in MASH Delta Sigma D/A Converters", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp , April

26 MASH topology x[k] ΣΔM 1 [k] r 1 [k] ΣΔM 2 [k] r 2 [k] ΣΔM 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Cascade first order sections Combine their outputs after they have passed through digital differentiators Advantage over single loop approach - Allows pipelining to be applied to implementation High speed or low power applications benefit 26

27 Calculation of STF and NTF for MASH topology (Step 1) x[k] ΣΔM 1 [k] r 1 [k] ΣΔM 2 [k] r 2 [k] ΣΔM 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Individual output signals of each first order modulator Addition of filtered outputs 27

28 Calculation of STF and NTF for MASH topology (Step 1) x[k] ΣΔM 1 [k] r 1 [k] ΣΔM 2 [k] r 2 [k] ΣΔM 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Overall modulator behavior - STF: H s (z) = 1 - NTF: H n (z) = (1 z -1 ) 3 28

29 The Issue of Intersymbol Interference 4I ref 2I ref I ref Clk(t) D 2 D 1 D 0 I 0 (t) (ideal) I 0 R V out C L I 0 (t) Dynamic operation of a non-return-to-zero (NRZ) DAC leads to inaccuracy due to transient effects - Transients only occur when the previous data is different We refer to this data dependent error as intersymbol interference Intersymbol interference especially poses a problem when using the DAC for data communication 29

30 Return-to-Zero (RZ) Signaling 4I ref 2I ref I ref Clk(t) D 2 D 1 D 0 I 0 (t) (ideal) I 0 V out R C L I 0 (t) Dynamic operation RZ DAC yields consistent results regardless of the pattern - Essentially, it inserts transients into every `1 value Issue half the signal swing is lost 30

31 Summary DAC structures can be implemented in a variety of ways - Resistors, currents, capacitors are all possible elements - Current-based DACS are the favorite for high frequency operation - Capacitor-based DACS are the favorite for low to modest frequency operation Key DAC specifications include offset, gain error, and non-linearity - Monotonocity is an import specification for DACs used within feedback loops Sigma-Delta modulators can be used to greatly increase the effective resolution of a DAC Dynamic operation of the DAC can lead to error due to intersymbol interference 31

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