ECE Department, Carnegie Mellon University, Pittsburgh, PA
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1 Bayesian odel Fusion: Large-Scale Perforance odeling of Analog and ixed-signal Circuits by Reusing Early-Stage Data Fa Wang, Wangyang Zhang, Shupeng Sun, Xin Li and Chenjie Gu ECE Departent, Carnegie ellon University, Pittsburgh, PA 5 Strategic CAD Labs, Intel Corporation, Hillsboro, OR 974 {fwang, wyzhang, shupengs, xinli}@ece.cu.edu, chenjie.gu@intel.co ABSTRACT Efficient high-diensional perforance odeling of today s coplex analog and ixed-signal (AS circuits with large-scale process variations is an iportant yet challenging task. In this paper, we propose a novel perforance odeling algorith that is referred to as Bayesian odel Fusion (BF. Our key idea is to borrow the siulation data generated fro an early stage (e.g., scheatic level to facilitate efficient high-diensional perforance odeling at a late stage (e.g., post layout with low coputational cost. Such a goal is achieved by statistically odeling the perforance correlation between early and late stages through Bayesian inference. Several circuit exaples designed in a coercial n COS process deonstrate that BF achieves up to 9 runtie speedup over the traditional odeling technique without surrendering any accuracy.. INTRODUCTION The aggressive scaling of integrated circuits (ICs leads to large-scale process variations that cannot be easily reduced by foundries. Process variations anifest theselves as the uncertainties associated with the geoetrical and electrical paraeters of seiconductor devices. These device-level variations significantly ipact the paraetric yield of analog and ixed-signal (AS circuits and, hence, ust be appropriately odeled, analyzed and optiized at all levels of design hierarchy []-[]. To address this variability issue, various techniques for perforance odeling have been developed during the past two decades []-[8]. The objective is to approxiate the circuit-level perforance (e.g., gain of an analog aplifier as an analytical (e.g., linear, quadratic, etc function of device-level variations (e.g., ΔV TH, ΔT OX, etc. Once such a perforance odel is available, it can be applied to a nuber of iportant applications such as estiating paraetric yield [9], extracting worst-case corner [], optiizing circuit design []-[5], etc. While perforance odeling was extensively studied in the past, the evolution of today s AS circuits has posed a nuber of new challenges in this area. In particular, the recent adoption of several eerging design ethodologies (e.g., reconfigurable analog design, adaptive post-silicon tuning, etc leads to highly coplex AS systes that integrate nuerous nanoscale devices. The rearkable increase of AS circuit size results in a two-fold consequence. Perission to ake digital or hard copies of all or part of this work for personal or classroo use is granted without fee provided that copies are not ade or distributed for profit or coercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific perission and/or a fee. DAC, ay 9 - June 7, Austin, TX, USA. Copyright AC //5...$5. High-diensional variation space: A large nuber of devicelevel rando variables ust be used to odel the process variations associated with a large-scale AS syste. For exaple, about 4 independent rando variables are required to odel the device isatches of a single transistor for a coercial n COS process. If an AS syste contains 4 transistors, there are about 4 5 rando variables in total to capture the corresponding device-level variations, resulting in a high-diensional variation space. In addition, it is extreely difficult, if not ipossible, to pre-select a subset of these rando variables for variation analysis, since the ipact of device isatches is circuit- and perforance-dependent. Expensive circuit siulation: The coputational cost of circuit siulation substantially increases, as the AS circuit size becoes increasingly large. For instance, it ay take a few days or even a few weeks to run the transistor-level siulation of a large AS circuit such as phase-locked loop or high-speed link. These recent trends of today s AS circuits ake perforance odeling extreely difficult. On one hand, a large nuber of siulation saples ust be generated in order to fit a high-diensional odel. On the other hand, creating a single sapling point by transistor-level siulation can take a large aount of coputational tie. The challenging issue here is how to ake perforance odeling coputationally affordable for today s large-scale AS circuits. This fundaental issue has not been appropriately addressed by the traditional perforance odeling techniques, e.g., the recent sparse regression algorith based on Orthogonal atching Pursuit (OP [8]. In this paper, we propose a new Bayesian odel Fusion (BF technique to facilitate large-scale perforance odeling of AS circuits. The proposed BF ethod is otivated by the fact that today s AS circuits are often designed via a ulti-stage flow. Naely, an AS design often spans three core stages: (i scheatic design, (ii layout design, and (iii chip anufacturing and testing. At each stage, siulation or easureent data are collected to validate the circuit design, before oving to the next stage. The traditional perforance odeling techniques rely on the data at a single stage only and they copletely ignore the data that are generated at other stages. The key idea of BF, however, is to reuse the early-stage data when fitting a late-stage perforance odel. As such, the perforance odeling cost can be substantially reduced. atheatically, the proposed BF ethod is derived fro the theory of Bayesian inference. Starting fro a set of early-stage (e.g., scheatic-level sapling points, BF first approxiates an early-stage perforance odel based on these saples. The early-stage odel is used as a teplate to define our prior knowledge for late-stage (e.g., post-layout perforance odeling. Specifically, a prior distribution is statistically defined for the late-stage odel coefficients. The prior knowledge is then cobined with very few late-stage sapling points to solve the
2 late-stage odel coefficients via Bayesian inference. Fro this point of view, by fusing the early-stage and late-stage perforance odels through Bayesian inference, we only need a sall nuber of late-stage sapling points to fit a highdiensional late-stage odel, thereby significantly reducing the coputational cost for perforance odeling. As will be deonstrated by our nuerical exaples in Section 5, BF achieves up to 9 runtie speedup over the traditional odeling technique without surrendering any accuracy. BF was previously proposed for paraetric yield estiation of AS circuits in [6] where Bayesian inference was used to estiate the probability distribution of AS perforance etrics. In this paper, we further extend the idea of BF to perforance odeling. It is iportant to ephasize that the forulation of our prior knowledge for perforance odeling is copletely different fro that shown in [6], as will be discussed in Section. The reainder of this paper is organized as follows. In Section, we review the iportant background on perforance odeling, and then derive our proposed BF ethod in Section. Several ipleentation issues are discussed in Section 4. The efficacy of BF is deonstrated by several circuit exaples in Section 5. Finally, we conclude in Section 6.. BACGROUND Given an AS circuit (e.g., an analog aplifier, its perforance (e.g., gain ay vary due to device-level variations (e.g., ΔV TH, ΔT OX, etc. The objective of perforance odeling is to approxiate the circuit perforance as an analytical function of the device-level variations: ( ( x f = x α ( g where f represents the perforance of interest, x is a vector containing the rando variables to odel device-level variations, {α ; =,,..., } denote the odel coefficients, {g (x; =,,..., } are the basis functions (e.g., linear or quadratic polynoials, and is the total nuber of basis functions. In order to deterine the perforance odel in (, we need to find the odel coefficients {α ; =,,..., }. Towards this goal, the traditional least-squares fitting ethod first generates a set of sapling points and then solves the odel coefficients fro the following linear equation [8]: G α = f ( where ( ( ( ( ( ( g x g x g x ( ( ( ( ( ( g x g x g x G = ( ( ( ( ( ( ( g x g x g x α α (4 5 ( ( [ ( f = f f f ] T. (5 In (-(5, x (k and f (k are the values of x and f(x at the kth sapling point respectively, and represents the total nuber of sapling points. The nuber of sapling points (i.e., should be greater than the nuber of unknown coefficients (i.e.,. As such, the linear equation in ( is overdeterined and the unknown odel coefficients {α ; =,,..., } are found by solving its least-squares solution. When the aforeentioned least-squares fitting ethod is applied to fit a high-diensional perforance odel with any 4 = [ α α ] T unknown odel coefficients, it requires a large nuber of sapling points to for the overdeterined linear equation in (. Note that each sapling point is generated by running an expensive transistor-level siulation. It, in turn, iplies that the least-squares fitting approach can be extreely expensive for high-diensional perforance odeling. Recently, sparse regression has been developed to address this coplexity issue [8]. The key idea is not to solve an overdeterined linear equation. Instead, the unknown odel coefficients are uniquely deterined by solving an underdeterined linear equation. This goal is achieved by exploiting the fact that ost odel coefficients of a highdiensional perforance odel are close to zero. In other words, the unknown odel coefficients carry a unique sparse pattern. The sparse regression algoriths were particularly developed to solve these sparse coefficients fro a sall nuber of sapling points. As such, the siulation cost of generating the required sapling points is greatly reduced. While sparse regression has been successfully applied to any practical applications, it still requires a large nuber of (e.g., sapling points to fit a high-diensional perforance odel [8]. Therefore, it reains ill-equipped for odeling largescale AS circuits where running a single transistor-level siulation to generate one sapling point ay take a few days or even a few weeks. otivated by this observation, we will propose a new BF technique in this paper to further reduce the nuber of required siulation saples and, hence, the coputational cost for large-scale perforance odeling.. BAYESIAN ODEL FUSION Siilar to sparse regression, the proposed BF ethod relies on the assuption that ost odel coefficients of a highdiensional perforance odel are close to zero. However, unlike the traditional sparse regression approach that fits the sparse perforance odel based on the siulation data at a single stage only (e.g., post-layout siulation data, BF attepts to identify the underlying sparse pattern by re-using the early-stage data (e.g., scheatic-level siulation data in order to efficiently fit a late-stage (e.g., post-layout perforance odel. In particular, BF consists of the following two ajor steps: (i statistically defining the prior knowledge of the sparse pattern based on the early-stage siulation data, and (ii optially deterining the late-stage perforance odel by cobining the prior knowledge and very few late-stage siulation saples. In this section, we will discuss the atheatical forulation of these two steps and highlight the novelty.. Prior nowledge Definition We consider two different perforance odels: the earlystage odel f E (x and the late-stage odel f L (x: 6 f E ( g ( x α (6 = E, x 7 f L ( g ( x α (7 = L, x where {α E, ; =,,..., } and {α L, ; =,,..., } represent the early-stage and late-stage odel coefficients, respectively. In (6-(7, we assue that the early-stage odel f E (x and the latestage odel f L (x share the sae basis functions. ore coplicated cases where f E (x and f L (x are approxiated by different basis functions will be further discussed in Section 4..
3 The early-stage odel f E (x is fitted fro the early-stage siulation data. In practice, the early-stage siulation data are collected to validate the early-stage design, before we ove to the next stage. For this reason, we should already know the earlystage odel f E (x before fitting the late-stage odel f L (x. Naely, we assue that the early-stage odel coefficients {α E, ; =,,..., } are provided as the input to our proposed BF ethod for late-stage perforance odeling. Given the early-stage odel f E (x, we first extract the prior knowledge that can be used to facilitate efficient late-stage odeling. To this end, we propose to learn the underlying sparse pattern for the late-stage odel f L (x based on the early-stage odel coefficients {α E, ; =,,..., }. Reeber that both the early-stage and late-stage odels are fitted for the sae perforance etric of the sae circuit. Their odel coefficients should be siilar. Naely, if the early-stage odel coefficient α E, has a large (or sall agnitude, it is likely that the late-stage odel coefficient α L, also has a large (or sall agnitude. Such prior knowledge should be atheatically encoded into our proposed perforance odeling flow. In this paper, we statistically represent the prior knowledge as a probability density function (PDF that is referred to as the prior distribution [9]. In particular, we odel each late-stage odel coefficient as a zero-ean Gaussian distribution: 8 pdf ( exp α L, α = ~ N(, σ L, π σ ( =,,, σ where the standard deviation σ is a paraeter that encodes the agnitude inforation of the odel coefficient α L,. If the standard deviation σ is sall, the prior distribution pdf(α L, is narrowly peaked around zero, iplying that the coefficient α L, is possibly close to zero. Otherwise, if the standard deviation σ is large, the prior distribution pdf(α L, widely spreads over a large range and the coefficient α L, can possibly take a value that is far away fro zero. Figure shows a siple exaple of our proposed prior distribution for two odel coefficients α L, and α L, where σ is sall and σ is large. pdf(α L, ~ N(, σ PDF pdf(α L, ~ N(, σ α L, or α L, Figure. A siple exaple of our proposed prior distribution is shown for two odel coefficients α L, and α L,. The coefficient α L, is possibly close to zero, since its prior distribution is narrowly peaked around zero. The coefficient α L, can possibly be far away fro zero, since its prior distribution widely spreads over a large range. Given (8, we need to appropriately deterine the standard deviation σ to fully specify the prior distribution pdf(α L,. The value of σ should be optiized so that the probability distribution pdf(α L, correctly represents our prior knowledge. In other words, by appropriately choosing the value of σ, the prior distribution pdf(α L, should take a large value (i.e., a high probability at the location where the actual late-stage odel coefficient α L, occurs. However, we only know the early-stage odel coefficient α E,, instead of the late-stage odel coefficient (8 α L,, at this oent. Reeber that α E, and α L, are expected to be siilar. Hence, the prior distribution pdf(α L, should also take a large value at α L, = α E,. Based on this criterion, the optial prior distribution pdf(α L, can be found by axiizing the probability for α E, to occur: 9 ax pdf ( α L, = α E, ( =,,,. (9 σ Naely, given the early-stage odel coefficient α E,, the optial standard deviation σ is deterined by the axiu likelihood estiation (LE in (9. To solve σ fro (9, we consider the following first-order optiality condition: d pdf ( α L, = α E, = ( =,,,. ( dσ Substituting (8 into ( yields: E E exp α, α, = π σ σ σ σ. ( ( =,,, The optial value of σ is equal to: = α ( =,, σ. ( E,, Eq. ( reveals an iportant fact that the optial standard deviation σ is siply equal to the absolute value of the earlystage odel coefficient α E,. This observation is consistent with our intuition. Naely, if the early-stage odel coefficient α E, has a large (or sall agnitude, the late-stage odel coefficient α L, should also have a large (or sall agnitude and, hence, the standard deviation σ should be large (or sall. To coplete the definition of the prior distribution for all latestage odel coefficients {α L, ; =,,..., }, we further assue that these coefficients are statistically independent and their joint distribution is represented as: ( α L, pdf α = L exp ( = σ π σ where ( = 4 [ ] T L = α L, α L, α L, α (4 contains all late-stage odel coefficients. The independence assuption in ( siply iplies that we do not know the correlation inforation aong these coefficients as our prior knowledge. The correlation inforation will be learned fro the late-stage siulation data, when the posterior distribution is calculated by the Bayesian inference in Section.. Finally, it is iportant to ention that the prior knowledge can be possibly defined as a distribution that is different fro (8. For exaple, the prior distribution is specified as a Gaussian distribution with non-zero ean in [6]. It, however, does not encode the sparse pattern of odel coefficients, as is the case of this paper. The efficacy of different prior definitions is casedependent. It reains an open question how to deterine the optial prior distribution for a specific perforance odeling proble where the circuit and perforance of interest are given. This proble will be further studied in our future research.. axiu-a-posteriori Estiation Once the prior distribution pdf(α L is derived in (, we will cobine pdf(α L with late-stage siulation saples {(x (k, f L (k ; k =,,, }, where x (k and f L (k are the values of x and f L (x at
4 the kth sapling point respectively, to solve the late-stage odel coefficient α L by axiu-a-posteriori (AP estiation. The key idea of AP is to find the posterior distribution [9], i.e., the conditional PDF pdf(α L f L where 5 ( ( [ ( f ] T L = f L f L f L (5 contains all late-stage siulation saples that are collected. Intuitively, the posterior distribution pdf(α L f L indicates the reaining uncertainty of α L, after we observe late-stage siulation saples. Here, since α L is a rando variable, it is described by a probability distribution, instead of a deterinistic value. AP attepts to find the optial value of α L to axiize the posterior distribution pdf(α L f L. Naely, it ais to find the solution α L that is ost likely to occur according to the posterior distribution. Based on Bayes theore, the posterior distribution pdf(α L f L is proportional to the prior distribution pdf(α L ultiplied by the likelihood function pdf(f L α L [9]: 6 pdf ( α L f L pdf ( α L pdf ( f L α L. (6 The prior distribution pdf(α L is already defined in (. To derive the likelihood function pdf(f L α L, we further assue that the error for the late-stage perforance odel f L (x follows a zeroean Gaussian distribution and, hence, the approxiate equality in (7 can be re-written as: 7 f L ( x = α L, g ( x + ε L (7 = where ε L denotes the odeling error with the distribution: ε L 8 pdf ( ε L exp ~ N (, σ π σ σ =. (8 In (8, the standard deviation σ controls the agnitude of the odeling error. Its value can be optially deterined by using the cross-validation technique that will be discussed in Section 4.. Given (7-(8, since the odeling error at the kth siulation saple (x (k, f (k L is siply one sapling point of the rando variable ε L, it follows the Gaussian distribution: 9 ( ( ( k ( k f α g x ~ N σ. (9 L = L,, Therefore, the probability of observing the kth sapling point is: ( ( ( k k exp α, fl L g x σ ( ( = k pdf f = L α L.( π σ Assue that all sapling points are independently generated, we can write the likelihood function pdf(f L α L as: ( α L ( ( k pdf = L α L pdf f L f. ( k= Cobining (, (6 and (-(, it is straightforward to prove that the posterior distribution pdf(α L f L is Gaussian and its covariance atrix Σ L and ean vector μ L are [7], [9]: T Σ [ ( ] L = σ G G + diag σ, σ,, σ ( T μ L = σ Σ L G f L ( where G and f L are defined by ( and (5 respectively, and diag( represents an operator to construct a diagonal atrix. Since the Gaussian PDF pdf(α L f L reaches its axiu at the ean value, the AP solution α L is equal to the ean vector μ L : T 4 α L = σ Σ L G f L. (4 In other words, Eq. (4 shows the optial coefficients solved by our proposed BF ethod for the late-stage perforance odel f L (x. While the basic idea of prior knowledge definition and axiu-a-posteriori estiation is illustrated in this section, several ipleentation issues ust be carefully considered in order to ake BF of practical utility. These ipleentation details will be further discussed in the next section. 4. IPLEENTATION ISSUES To ake the proposed BF ethod of practical utility, two ipleentation issues, (i issing prior knowledge and (ii crossvalidation, ust be carefully considered. In this section, we will discuss these ipleentation issues in detail. 4. issing Prior nowledge The BF ethod derived in Section assues that the earlystage odel f E (x and the late-stage odel f L (x share the sae basis functions. In practice, this assuption ay not always hold, because the early-stage odel does not necessarily capture all the detailed behaviors of a circuit. For instance, it is well-known that layout parasitics will be added to the post-layout netlist (late stage during layout extraction. The variations of these parasitics ust be odeled by a nuber of new rando variables that are copletely ignored at the scheatic level (early stage. The latestage post-layout odel f L (x should contain additional basis functions corresponding to the new rando variables that are not found fro the early-stage scheatic odel f E (x. In this case, the early-stage odel f E (x does not carry any prior knowledge about the late-stage odel coefficients associated with these additional basis functions. In other words, the prior knowledge for these latestage odel coefficients is issing. To appropriately handle the cases with issing prior knowledge, we re-visit the prior distribution pdf(α L, defined in (8. As entioned in Section., the standard deviation σ of the Gaussian distribution pdf(α L, encodes the agnitude inforation of the late-stage odel coefficient α L,. If there is no prior knowledge available for α L,, it iplies that the late-stage odel coefficient α L, can possibly take any value with equal probability. Hence, the standard deviation σ should be set to + : 5 σ = + (5 so that the prior distribution is nearly constant over a wide range. Note that when calculating the posterior distribution in (-(, only the value of σ is needed. Hence, the infinite standard deviation in (5 would not cause any nuerical proble for solving the late-stage odel coefficients. 4. Cross-Validation As entioned in Section., the standard deviation σ of the odeling error in (8 ust be deterined. Otherwise, without knowing σ, the late-stage odel coefficients α L cannot be deterined by the AP solution in (4. The objective here is to find the optial value of σ so that the odeling error is iniized. Towards this goal, we ust accurately estiate the odeling error for different σ values and then select the optial σ with inial error. To quantitatively estiate the odeling error for a given σ value, we adopt the idea of N-fold cross validation fro the statistics counity [9]. Naely, we partition the entire data set 4
5 into N groups. odeling error is estiated fro N independent runs. In each run, one of the N groups is used to estiate the odeling error and all other groups are used to calculate the odel coefficients. Note that the training data for coefficient estiation and the testing data for error estiation are not overlapped. Hence, over-fitting can be easily detected. In addition, different groups should be selected for error estiation in different runs. As such, each run results in an error value e n (n =,,..., N that is easured fro a unique group of data points. The final odeling error is coputed as the average of {e n ; n =,,..., N}, i.e., e = (e + e e N /N. ore details on cross-validation can be found in [9]. 4. Suary Algorith suarizes the ajor steps of our proposed BF ethod. It consists of two core coponents: (i prior distribution definition, and (ii AP estiation. The efficacy of BF will be further deonstrated by our nuerical exaples in the next section. Algorith : Bayesian odel Fusion (BF. Start fro the early-stage perforance odel f E (x in (6.. Define the prior distribution for the late-stage odel coefficients {α L, ; =,,..., } by (-( and (5.. Collect late-stage siulation saples {(x (k, f (k L ; k =,,, }. 4. Solve the late-stage odel coefficients {α L, ; =,,..., } based on (4 where σ is deterined by cross-validation. 5. NUERICAL EXAPLES In this section, several circuit exaples designed in a coercial n COS process are used to deonstrate the efficacy of the proposed BF ethod. Our objective is to build post-layout perforance odels for these circuits. For testing and coparison purposes, two different perforance odeling techniques are ipleented: (i the traditional sparse regression ethod based on OP [8], and (ii the proposed BF ethod. Here, the OP algorith is chosen for coparison, since it is one of the state-of-the-art techniques in the literature. When ipleenting BF, we use the scheatic-level siulation data to define our prior knowledge for post-layout perforance odeling. In each exaple, two different data sets, referred to as the training set and the testing set respectively, are generated by rando sapling based on post-layout transistor-level siulation. The training set is used for coefficient fitting, including crossvalidation. The testing set contains independent rando saples that are used for odel validation. All nuerical experients are run on a.9ghz Linux server with 4GB eory. 5. Ring Oscillator Shown in Figure (a is the siplified circuit scheatic of a ring oscillator designed in a coercial n COS process. In this exaple, there are 777 independent rando variables in total to odel device-level process variations, including both inter-die variations and rando isatches. Our objective is to approxiate three post-layout perforance etrics, power, frequency and phase noise, as linear functions of these 777 rando variables. Figure (b-(d show how the perforance odeling error varies with the nuber of post-layout training saples. Note that for both OP and BF, the odeling error decays as the nuber of saples increases. However, given the sae nuber of postlayout training saples, BF is able to achieve substantially higher accuracy than OP, especially if only few saples are available. Table further copares the odeling error and cost for OP and BF. The total cost for perforance odeling consists of two ajor portions: (i siulation cost (i.e., the cost of running a transistor-level siulator to generate all post-layout saples in the training set, and (ii fitting cost (i.e., the cost of solving all unknown odel coefficients. As shown in Table, the total odeling cost is doinated by transistor-level siulation in this exaple. BF achieves 9 runtie speed-up over OP without surrendering any accuracy. odeling Error (%.5.5 (a OP (Traditional BF (Proposed Nuber of Post-Layout Saples (b. OP (Traditional BF (Proposed Nuber of Post-Layout Saples Nuber of Post-Layout Saples (c (d Figure. A ring oscillator designed in a coercial n COS process is used as an exaple for perforance odeling where BF requires significantly less post-layout saples than OP to achieve the sae accuracy: (a siplified circuit scheatic of the ring oscillator, (b odeling error for power, (c odeling error for frequency, and (d odeling error for phase noise. Table. Perforance odeling error and cost for ring oscillator OP (Traditional BF (Proposed # of post-layout training saples 9 odeling error for power.77%.7% odeling error for frequency.65%.54% odeling error for phase noise.%.% Siulation cost (Hour.58.4 Fitting cost (Second Total odeling cost (Hour.58.4 odeling Error (% odeling Error (% 5. SRA Read Path Figure (a shows the siplified circuit scheatic of an SRA read path designed in a coercial n COS process. In this exaple, there are 667 independent rando variables to odel device-level process variations. Read delay is our circuit perforance of interest, and it is approxiated as a linear function of all device-level rando variables. Figure (b and Table copare the odeling error and cost for OP and BF. Siilar to the ring oscillator exaple, two iportant observations can be ade here. First, BF requires substantially less post-layout training saples than OP, in order. OP (Traditional BF (Proposed 5
6 to achieve the sae odeling accuracy. In this exaple, BF reduces the nuber of required saples fro 4 to without surrendering any accuracy. Figure 4 further plots the histogras of odeling error for both OP and BF with 4 and postlayout training saples, respectively. Second, but ore iportantly, since the total odeling cost is doinated by transistor-level siulation, BF successfully reduces the total odeling cost by reducing the nuber of required post-layout training saples. Copared to OP, BF achieves 4 runtie speed-up, as shown in Table. Tiing logic Nuber of Post-Layout Saples (a (b Figure. A siplified SRA read path designed in a coercial n COS process is used as an exaple for perforance odeling where BF requires significantly less post-layout saples than OP to achieve the sae accuracy: (a siplified circuit scheatic of the SRA read path, and (b odeling error for read delay. Table. Perforance odeling error and cost for SRA OP (Traditional BF (Proposed # of post-layout training saples 4 odeling error for read delay.%.99% Siulation cost (Hour Fitting cost (Second.56. Total odeling cost (Hour Nuber of Saples 5 4 odeling Error (% Nuber of Saples 6. CONCLUSIONS In this paper, a novel BF algorith is proposed for efficient high-diensional perforance odeling of coplex AS circuits with consideration of large-scale process variations. BF borrows the early-stage (e.g., scheatic-level siulation data to learn a odel teplate that is statistically represented as a prior distribution. Next, the odel teplate encoding our prior knowledge is further calibrated by very few late-stage (e.g., postlayout siulation saples to accurately create a late-stage perforance odel. As such, the coputational cost of highdiensional perforance odeling can be substantially reduced, since only few transistor-level siulations are required at the late 4 OP (Traditional BF (Proposed odeling Error (% odeling Error (% (a (b Figure 4. Histogras of odeling error are estiated fro the testing set for read delay: (a odeling error of OP with 4 post-layout training saples, and (b odeling error of BF with post-layout training saples. 5 4 stage. As is deonstrated by our circuit exaples designed in a coercial n COS process, the proposed BF ethod achieves up to 9 runtie speedup copared to the traditional odeling technique. In our future work, we will further apply BF to several practical applications such as statistical analysis of large-scale AS systes. 7. ACNOWLEDGEENTS This work has been supported in part by National Science Foundation and Intel Corporation. 8. REFERENCES [] Seiconductor Industry Associate, International Technology Roadap for Seiconductors,. [] X. Li, J. Le and L. Pileggi, Statistical Perforance odeling and Optiization, Now Publishers, 7. [] Z. Feng and P. Li, Perforance-oriented statistical paraeter reduction of paraeterized systes via reduced rank regression, IEEE ICCAD, pp , 6. [4] A. Singhee and R. Rutenbar, Beyond low-order statistical response surfaces: latent variable regression for efficient, highly nonlinear fitting, IEEE DAC, pp. 56-6, 7. [5] A. itev,. arefat, D. a and J. Wang, Principle Hessian direction based paraeter reduction for interconnect networks with process variation, IEEE ICCAD, pp. 6-67, 7. [6] T. cconaghy and G. Gielen, Teplate-free sybolic perforance odeling of analog circuits via canonical-for functions and genetic prograing, IEEE Trans. on CAD, vol. 8, no. 8, pp. 6-75, Aug. 9. [7] T. cconaghy, High-diensional statistical odeling and analysis of custo integrated circuits, IEEE CICC,. [8] X. Li, Finding deterinistic solution fro underdeterined equation: large-scale perforance odeling of analog/rf circuits, IEEE Trans. on CAD, vol. 9, no., pp , Nov.. [9] X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, Asyptotic probability extraction for nonnoral perforance distributions, IEEE Trans. on CAD, vol. 6, no., pp. 6-7, Jan. 7. []. Sengupta, S. Saxena, L. Daldoss, G. raer, S. inehane and J. Cheng, Application-specific worst case corners using response surfaces and statistical odels, IEEE Trans. on CAD, vol. 4, no. 9, pp. 7-8, 5. [] Z. Wang and S. Director, An efficient yield optiization ethod using a two step linear approxiation of circuit perforance, IEEE EDAC, pp , 994. [] A. Dharchoudhury and S. ang, Worse-case analysis and optiization of VLSI circuit perforance, IEEE Trans. on CAD, vol. 4, no. 4, pp , Apr [] G. Debyser and G. Gielen, Efficient analog circuit synthesis with siultaneous yield and robustness optiization, IEEE ICCAD, pp. 8-, 998. [4] F. Schenkel,. Pronath, S. Zizala, R. Schwencker, H. Graeb and. Antreich, isatch analysis and direct yield optiization by spec-wise linearization and feasibility-guided search, IEEE DAC, pp ,. [5] X. Li, P. Gopalakrishnan, Y. Xu and L. Pileggi, Robust analog/rf circuit design with projection-based perforance odeling, IEEE Trans. on CAD, vol. 6, no., pp. -5, Jan. 7. [6] X. Li, W. Zhang, F. Wang, S. Sun and C. Gu, Efficient paraetric yield estiation of analog/ixed-signal circuits via Bayesian odel fusion, IEEE ICCAD,. [7] S. Ji, Y. Xue, and L. Carin, Bayesian copressive sensing, IEEE Trans. on Signal Processing, pp , Jun. 8. [8] R. yers and D. ontgoery, Response Surface ethodology: Process and Product Optiization Using Designed Experients, Wiley-Interscience,. [9] C. Bishop, Pattern Recognition and achine Learning, Springer, 6. 6
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