ENABLING SOLUTIONS FOR FABLESS I/O DESIGN SEPTEMBER 2015

Transcription

1 ENABLING SOLUTIONS FOR FABLESS I/O DESIGN SEPTEMBER 2015

2 Sofics is a foundry-independent IP provider Semiconductor IP provider Sofics = Solutions for ICs IP portfolio Since 2000: On-chip ESD protection for CMOS, SOI applications up to 5V Since 2010: On-chip ESD protection for applications 5V to 100V New (non-esd) portfolio s under development Consulting On-chip ESD protection support Test lab ESD relevant analysis Transmission Line Pulsers, HBM, MM, Latch-up, IEC SOFICS 2015 Proprietary & Confidential 2

3 Sofics on-chip ESD clamps protect a broad range of applications and technologies 1 IC release per day includes Sofics on-chip ESD protection 50+ different processes including CMOS down to 28nm, BCD, SOI fabless customers include Sofics ESD IP for beyond standard IOs 70+ customers protect chip interfaces with Sofics ESD 75+ patents in Sofics clean ESD IP portfolio SOFICS 2015 Proprietary & Confidential 3

4 50+ Sofics fabless customers testify to the need for ESD solutions complementary to the foundry SOFICS 2015 Proprietary & Confidential 4

5 Specialty ESD clamps available Broad solution coverage on TSMC technology Portable to other nodes/domains/foundries Node 350nm HV 250nm BCD, gen. I and II 180nm BCD, gen. I and II 180nm CMOS 130nm CMOS Voltage domains 3.3V, 15V 12V, 24V, 40V, 60V >>> PowerQubic license TSMC-Sofics 18V, 24V, 32V, 40V, 60V 1.8V, 3.3V, 5V 1.0V, 1.2V, 3.3V, 5V, 7V 90nm CMOS 1.2V, 1.8V, 3.3V 65nm CMOS 40nm CMOS 28nm CMOS 1.0V, 1.2V, 1.8V, 2.5V, 3.3V, 5V 0.9V, 1.2V, 1.8V, 3.3V, 5V 0.85V, 0.9V, 1.8V, 3.3V, 5V, 5.5V, 12V 16nm FinFET Taped out ESD test chip (July 2015) SOFICS 2015 Proprietary & Confidential 5

6 TakeCharge: ESD solutions for up to 5V CMOS >50 customers, broad application space, various foundries High speed digital interfaces USB, HDMI up to 6Gbps, SerDes up to 28Gbps Wireline communication, optical communication, several Gbps Wireless applications (GPS, NFC, bluetooth...) up to 10 GHz FPGA IO protection in 180nm to 28nm CMOS Smartcard, security, M2M applications Generic ASIC protection libraries Power Management ICs Computing applications Ultra low power MCUs Image processors CMOS Imager sensors Medical applications... SOFICS 2015 Proprietary & Confidential 6

7 PowerQubic ESD solutions for High Voltage interfaces >20 product implementations Several customers >20 projects Different product types supported Automotive LIN Transceivers Automotive sensors (Temp, humidity, Air flow) Automotive LED drivers Industrial CAN interface Industrial DAC Industrial High Voltage RS485 Li-ion battery control Switching/power regulator Hearing implant interface protection SOFICS 2015 Proprietary & Confidential 7

8 3 reasons why fabless companies use Sofics 1. Enable specialty or advanced I/O performance ٧ Lower power ٧ Higher speed ٧ Less noise ٧ Overvoltage tolerance 2. Enhanced robustness for harsher specs ٧ Withstand 5x.. 15x common stress levels where needed ٧ Integrated ESD EOS LU IEC solutions ٧ Smaller area, longer battery life 3. Reduce design and silicon cost ٧ Solutions proven in more than 3,000 product ICs ٧ 180nm down to 16nm, CMOS bulk/soi/finfet ٧ Cost effective: no additional implant or blocking layers ٧ Smaller silicon dies; no termination overhead SOFICS 2015 Proprietary & Confidential 8

9 How can Sofics reduce my IC cost? Frequently asked question How can Sofics reduce my cost? Answer The amount of cost saving depends on a number of factors Technology node (targeted) manufacturing volume Planning (direct to mass production, engineering sample / MPW runs first?) Cost per wafer All ESD solutions available by the foundry or not? Total silicon area occupied by ESD Examples further in this document SOFICS 2015 Proprietary & Confidential 9

10 Part 1: Foundry ESD is not free Free ESD from the foundry can cost a lot The foundry ESD does not cover all cases. It is possible that additional development is required (MPW, time delay) to create new solutions: Cost: $ time to market increase by several months Potential of increased die size due to larger ESD solutions Cost: 1% to 10% Can run over $1M over the entire product life time not really free! If the foundry ESD solution fails you need additional costs for MPW run or additional mask set Cost: $ (MPW run) to $ (full mask set) and additional delays. Reduced market because foundry ESD puts limitations on the IC performance: maximum speed, maximum frequency, power consumption, voltage limitations Customer is locked to one foundry and can thus not benefit from overflow production at low-cost wafer fabs, reducing negotiation power, reducing flexibility to respond to changes in the market. SOFICS 2015 Proprietary & Confidential 10

11 Part 2: Real costs of IC design and production Creating a new IC costs a lot different categories: Design the product IC Prototype through MPW Buying final masks Manufacturing at the foundry Insurances All of these costs differ for different applications and technology nodes SOFICS 2015 Proprietary & Confidential 11

12 A. Design of a new product IC Several costs for a new design EDA cost Design time / manpower Licensing IP blocks (with one-time fees) Rising cost for newer technologies Example: About $60M for a new 40nm design. Option to reduce cost: Reuse designs (product family) so that in average the design cost will reduce. SOFICS 2015 Proprietary & Confidential 12

13 B. Prototype Most companies run MPW prototypes Companies tend to use MPW runs for engineering samples to try out the functionality before buying the expensive masks Sometimes they can use MPW runs for initial parts and sampling to customers. SOFICS 2015 Proprietary & Confidential 13

14 C. Buying full mask set Masks are getting very expensive at advanced nodes It must be first time right... If there is a problem with the chip, it can cost a million $ to resolve the problem (new full mask set). Of course if it can be solved with one mask only then it can be reduced by a factor of 10-20, still ~100K in advanced CMOS On top of the additional cost for new masks is the cost to find the problem and most importantly the delay to market introduction SOFICS 2015 Proprietary & Confidential 14

15 D. Manufacturing at the foundry Foundry customers pay for every wafer Wafers get really expensive at advanced nodes Typically the yield is also lower at advanced nodes... SOFICS 2015 Proprietary & Confidential 15

16 E. Insurance cost Companies need to pay insurance... If a design company creates its own ESD design solution it must make sure they can really use that solution! Companies need to take some insurance to prevent all kinds of issues. Typical issue: IP infringement risk certainly big companies can be a likely target There have been cases where 2 major companies have been in court over ESD designs SOFICS 2015 Proprietary & Confidential 16

17 How can these costs be reduced? There are thus several categories to reduce cost Design, development cost Mask cost reduction Manufacturing cost Risk reduction SOFICS 2015 Proprietary & Confidential 17

18 A. Design cost reduction Selecting the right ESD Sofics can reduce the NRE design cost. If the IC company needs a special ESD protection that is not covered by the foundry then they need to run an MPW to create a new ESD clamp solution. If a company plans to run a MPW to develop its own ESD solution it can cost $100K for advanced CMOS and the time to market is extended by several months. Sofics can deliver silicon proven solutions that can be integrated into full SoC designs without the need for further MPW runs: Save $50k to $100k Reduce time to market by several months SOFICS 2015 Proprietary & Confidential 18

19 B. Mask cost reduction Selecting the right ESD... Foundry ESD solutions typically require special processing ESD implant masks is typically used at advanced nodes Other examples: Silicide blocking mask, NLDD block mask Reduced mask count / process steps Sofics can help remove the ESD implant mask. That can reduce cost of $50 per wafer (1% to 5% cost reduction) In some cases the silicide blocking mask can be removed another $50 per wafer SOFICS 2015 Proprietary & Confidential 19

20 C. Manufacturing cost reduction Selecting the right ESD... Smaller IC through smaller ESD solutions. If Sofics can reduce the total area by a few percent the IC design company can win because Sofics royalty charge is less than 1% of the wafer price. Many years ago we worked with companies active in Display Drivers business (Link). We provided ESD solutions to several companies. Example: In one case we could reduce the total chip area by 12% just by changing to Sofics ESD. Example: Recent case in 180nm BCD ESD from Sofics is 40% smaller than foundry solution The company is able to reduce wafer manufacturing cost by 1.6 million dollar over the product lifetime only by changing the foundry ESD to smaller Sofics ESD solutions SOFICS 2015 Proprietary & Confidential 20

21 28nm example: design information IC production cost calculations 28nm 12 wafer price: $5800 Chip size: 17mm x 17mm = 289mm² Planned production of 400,000 IC s for that IC Core area (non-esd) is set at 91.5%, IO area (including ESD, >950 IOs) is set at 8% Total ESD area (clamps, RC, trigger, boost) is below 5% of the total area Summary for current design About 185 chips on a wafer Production volume corresponds to 2163 wafers Unit chip cost for silicon (production only): $31.4 SOFICS 2015 Proprietary & Confidential 21

22 28nm example: Sofics ESD solution Sofics ESD solution: smaller ESD solution Area reduction depends on the specific IO type Calculation based on spread of IO types and possible area savings. Summary for design using Sofics ESD clamps Chip size reduced by 10.2 mm² (3.5%) 197 chips on a wafer 12 additional ICs per wafer Production volume corresponds to 2031 wafers 132 wafers less Production cost reduction by $765,000 Royalty cost (2500 wafer block) to Sofics: $ Gain for customer: $ SOFICS 2015 Proprietary & Confidential 22

23 D. Risk reduction Selecting the right ESD Sofics IP comes with guarantees. We check every new ESD patent we look for new ESD submissions The risk of IP infringement due to ESD is thus strongly reduced. SOFICS 2015 Proprietary & Confidential 23

24 Conclusion Selecting Sofics ESD can really reduce your IC cost Solutions proven in more than 3,000 product ICs 180nm down to 16nm, CMOS bulk/soi/finfet Cost effective: no additional implant or blocking layers Smaller silicon dies; no termination overhead Reduced risks SOFICS 2015 Proprietary & Confidential 24

25 Contact us Sofics representative in China XMOD Shanghai Sofics contacts Bart Keppens Benjamin Van Camp Koen Verhaege SOFICS bvba RPR Groendreef 31, 9880 Aalter, Belgium (tel) , (fax) PowerQubic, TakeCharge, Sofics are registered trademarks of Sofics bvba SOFICS 2015 Proprietary & Confidential 25