IRLB8721PbF. V DSS R DS(on) max Qg (typ.) 30V GS = 10V 7.6nC. HEXFET Power MOSFET. Absolute Maximum Ratings. Thermal Resistance.
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1 PD Applications l Optimized for UPS/Inverter Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Benefits l Very Low RDS(on) at 4.5V l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current l Lead-Free HEXFET Power MOSFET V DSS R DS(on) max Qg (typ.) 30V 8.7m:@ = V 7.6nC D S D G TO-220AB G D S Gate Drain Source Absolute Maximum Ratings V DS I T C = 25 C I T C = 0 C I DM P C = 25 C P C = 0 C T J T STG Drain-to-Source Voltage Gate-to-Source Voltage Parameter Continuous Drain V Continuous Drain V Pulsed Drain Current c Maximum Power Dissipation g Maximum Power Dissipation g Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for seconds Mounting torque, 6-32 or M3 screw Max. 30 ± to (.6mm from case) lbxin (.Nxm) Units V A W W/ C C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case g 2.3 R θcs Case-to-Sink, Flat Greased Surface 0.5 C/W R θja Junction-to-Ambient f 62 Notes through are on page 9 4/22/09
2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 30 V = 0V, I D = 250μA ΔΒV DSS /ΔT J Breakdown Voltage Temp. Coefficient 2 mv/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance mω = V, I D = 3A e 3. 6 = 4.5V, I D = 25A e (th) Gate Threshold Voltage V V DS =, I D = 25μA Δ(th) /ΔT J Gate Threshold Voltage Coefficient -7.0 mv/ C I DSS Drain-to-Source Leakage Current.0 μa V DS = 24V, = 0V 50 V DS = 24V, = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 0 na = 20V Gate-to-Source Reverse Leakage -0 = -20V gfs Forward Transconductance 35 S V DS = 5V, I D = 25A Q g Total Gate Charge Q gs Pre-Vth Gate-to-Source Charge.9 V DS = 5V Q gs2 Post-Vth Gate-to-Source Charge.2 nc = 4.5V Q gd Gate-to-Drain Charge 3.4 I D = 25A Q godr Gate Charge Overdrive 2.0 See Fig. 6 Q sw Switch Charge (Q gs2 Q gd ) 4.6 Q oss Output Charge 7.9 nc V DS = 5V, = 0V R G Gate Resistance Ω t d(on) Turn-On Delay Time 9. V DD = 5V, = 4.5Ve t r Rise Time 93 I D = 25A t d(off) Turn-Off Delay Time 9.0 ns R G =.8Ω t f Fall Time 7 See Fig. 4 C iss Input Capacitance 77 = 0V C oss Output Capacitance 360 pf V DS = 5V C rss Reverse Transfer Capacitance ƒ =.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 98 mj I AR Avalanche Currentc 25 A Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 62 (Body Diode) A I SM Pulsed Source Current 250 (Body Diode)c V SD Diode Forward Voltage.0 V t rr Reverse Recovery Time 6 24 ns Q rr Reverse Recovery Charge 4 2 nc MOSFET symbol showing the integral reverse Conditions Conditions p-n junction diode. T J = 25 C, I S = 25A, = 0V e T J = 25 C, I F = 25A, V DD = 5V di/dt = 200A/μs e 2
3 I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 00 0 VGS TOP V 9.0V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 3.0V 00 0 VGS TOP V 9.0V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 3.0V 3.0V 3.0V 60μs PULSE WIDTH Tj = 25 C μs PULSE WIDTH Tj = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 25A = V 0.5 T J = 75 C T J = 25 C.0 V DS = 5V 60μs PULSE WIDTH , Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3
4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf), Gate-to-Source Voltage (V) = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss 4 2 I D = 25A V DS = 24V V DS = 5V Coss 8 0 Crss V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) 0 T J = 75 C 0 0μsec msec msec T J = 25 C = 0V V SD, Source-to-Drain Voltage (V) T C = 25 C T J = 75 C Single Pulse V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4
5 I D, Drain Current (A) (th) Gate threshold Voltage (V) I D =.0mA I D = 250μA I D = 25μA T C, CaseTemperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Threshold Voltage vs. Temperature D = 0.50 Thermal Response ( Z thjc ) SINGLE PULSE ( THERMAL RESPONSE ) τj τj τ τ Ci= τi/ri Ci i/ri R R 2 R 3 R R 2 R 3 τ 2 τ 3 τ 2 τ 3 E-006 E t, Rectangular Pulse Duration (sec) R4 R4 τ4 τ4 τc τ Ri ( C/W) τι (sec) E Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5
6 R DS(on), Drain-to -Source On Resistance (mω) E AS, Single Pulse Avalanche Energy (mj) I D = 3A 300 I D TOP 5.4A A BOTTOM 25A T J = 25 C T J = 25 C , Gate -to -Source Voltage (V) Starting T J, Junction Temperature ( C) Fig 2. On-Resistance vs. Gate Voltage Fig 3a. Maximum Avalanche Energy vs. Drain Current 5V tp V (BR)DSS V DS L DRIVER R G 20V tp D.U.T IAS 0.0Ω - V DD A Fig 3b. Unclamped Inductive Test Circuit I AS Fig 3c. Unclamped Inductive Waveforms V DS R D D.U.T. V DS 90% R G - V DD Pulse Width µs Duty Factor 0. % % t d(on) t r t d(off) t f Fig 4a. Switching Time Test Circuit Fig 4b. Switching Time Waveforms 6
7 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * = 5V for Logic Level Devices Fig 5. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Current Regulator Same Type as D.U.T. Id Vds 2V.2μF 50KΩ.3μF Vgs D.U.T. V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgodr Qgd Qgs2 Qgs Fig 6a. Gate Charge Test Circuit Fig 6b. Gate Charge Waveform 7
8 TO-220AB Package Outline (Dimensions are shown in millimeters (inches)) TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: 8
9 TO-220AB Part Marking Information EXAMPLE: T HIS IS AN IRF LOT CODE 789 AS SEMBLED ON WW 9, 2000 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead - Free" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE PART NUMBER DAT E CODE YEAR 0 = 2000 WEEK 9 LINE C Note: For the most current drawing please refer to IR website at: Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.32mH, R G = 25Ω, I AS = 25A. ƒ Pulse width 400μs; duty cycle 2%. When mounted on " square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. R θ is measured at T J approximately 90 C. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.04/
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