Examine soft-core processors for embedded systems

Transcription

1 Examine soft-core processors for embedded systems Here's a closer look at four soft-core processors to see which one would be most suitable for your platform. By Sven-Ake Andersson Senior ASIC/FPGA designer Realtime Embedded When designing an embedded system in a FPGA, we will most likely need some form of controller in our system. This controller can be a simple microcontroller or a fully-fledged microprocessor running the Linux operating system. But before we make this decision, let s first consider the various options that are available to us. One solution is to use an off-the-shelf (OTS) microprocessor mounted on the board and connecting to the FPGA using a standard bus like AMBA. In fact, this still appears to be the most commonly-used solution. There are times, however, where an OTS processor-based approach will not meet our requirements. An example would be an application that requires peripheral functionality that is not available in a discrete solution, or where board real estate is limited. Another option is to embed a hard processor core on the chip. A hard processor core has dedicated silicon area on the FPGA. This allows it to operate with a core frequency similar to that of a discrete microprocessor. Examples of hard processor cores used in FPGAs are the PowerPC used in Virtex-4/5 and the ARM Cortex-A9 dual-core MCU used in the new Zynq-7000 All Programmable SoC from Xilinx. Unfortunately, a hard processor core does not provide the ability to adjust it to better meet the needs of the application, nor does it allow for the flexibility of adding a processor to an existing FPGA design or adding an additional processor to provide more processing capabilities. A soft-core processor solution is one that is implemented entirely in the logic primitives of an FPGA. Because of this implementation, the processor will not operate at the same clock frequencies or have the same performance of a discrete solution. In many embedded applications, however, the high performance achieved by the previous two processing options is not required, and performance can be traded for expanded functionality, reduced cost, and flexibility. All the major FPGA vendors have soft-core processors in their product offerings and there are also a number of companies and organisations developing soft-core processors that are platform independent and can be implemented in any FPGA design. Choosing a soft-core processor When commencing an FPGA design project that will employ a soft-core processor, it can be hard to decide which processor to use. To help you with this decision and give you quick start guide, let s take a closer look at four softcore processor to see which one would be most suitable for your platform. Here are the four candidates we will investigate: LEON3 MicroBlaze Nios II OpenRISC Prerequisites Our system will be built on a standard FPGA development board. We will use the CAE tools that are suggested by the processor provider and try to use licence-free tools as much as possible. When there are no free tools available, we will use an evaluation licence from the FPGA vendor. The system must be able to run a Linux operating system and a Real Time Operating System (RTOS). The performance of the processor cores will be measured by using the benchmark program CoreMark. CPU core benchmarking Although it doesn t reflect how you would use a processor in a real application, sometimes it s important to isolate the CPU s core from the other elements of the processor and focus on one key element. For example, you might want to have the ability to ignore memory and I/O effects and focus primarily on the pipeline operation. CoreMark is capable of testing a processor s basic pipeline structure; it also provides the ability to test basic read/write operations, integer operations, and control operations. EE Times-Asia eetasia.com Copyright 2013 emedia Asia Ltd. Page 1 of 5

2 Installing Linux We will use the Linux distribution recommended by the processor vendor. An embedded system that is going to run Linux must include some specific hardware blocks. In a typical system we find the following: CPU with memory management unit (MMU) Instruction and data caches DDR3 memory interface Debug module Interrupt controller Ethernet controller DIP switches, LEDs and push button interface SPI flash interface Timer UART Clock generator and system reset logic The LEON3 The LEON3 is a synthesisable VHDL model of a 32bit processor compliant with the SPARC V8 architecture developed by Aeroflex Gaisler AB in Sweden. The model is highly configurable and particularly suitable for systemon-a-chip (SOC) designs. The full source code is available under the GNU GPL licence, allowing free and unlimited use for research and education. The LEON project was started by the European Space Agency (ESA) in late 1997 to study and develop a highperformance processor to be used in European space projects. The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. No licences are required for research and education use. All RTL source code is available Fast support Linux and RTOS can be installed Not all FPGA development boards are supported. Not in widespread use The complete design environment for the LEON3, including all the IP cores, can be downloaded from the Gaisler Aeroflex webpage ( The AMBA-2.0 AHB/APB bus has been selected as the common on-chip bus due to its market dominance (ARM processors) and because it is well documented and can be used for free without licence restrictions. The LEON3 can be easily configured using a graphical user interface. EE Times-Asia eetasia.com Copyright 2013 emedia Asia Ltd. Page 2 of 5

3 The MicroBlaze The 32bit MicroBlaze soft processor core from Xilinx is a classic RISC architecture. It was originally developed around the end of 2000 and the beginning of 2001, and it was released later that year. Thereafter, the MicroBlaze has continued to evolve with new functions being added on a regular basis. For example, the most recent release, version 8.20, is equipped with the new AXI bus interface. Can be used in all Xilinx FPGA families Lots of configuration options Uses the AXI standard bus Can be used only in Xilinx FPGAs EDK needs a licence Source code not available Xilinx Linux support is very basic (this may change now that they have bought PetaLogix) The MicroBlaze soft-core processor is fully integrated in the Xilinx FPGA design environment. It can easily be configured for many different applications from a simple controller to a fully-fledged Linux processor. The Xilinx EDK environment makes it very easy to configure the processor and add all the peripherals needed to build a complete processor system. The OpenRISC The OpenRISC project was started in 1999 by a group of Slovenian university students. Their aim was to create an open source microprocessor architecture specification and implementation. Two years later, they had produced a complete architectural specification, architectural simulator, and Verilog HDL implementation and made everything publicly available through their new open hardware community, OpenCores. The OpenRISC 1200 (OR2100) is a synthesisable CPU core maintained by the developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL). Everything is open source. RTL source code is available. The ORPSoC reference platform makes it easy to implement an OpenRISC system The GNU toolchain is fully supported A large user community can help solve problems Few FPGA development boards are supported Complicated debug solutions The Wishbone bus is somewhat outdated The OpenCores website is confusing Many IP blocks are not maintained EE Times-Asia eetasia.com Copyright 2013 emedia Asia Ltd. Page 3 of 5

4 Using the OpenRISC 1200 soft-core processor is a mixed bag. It is hard to find the way through the OpenCores website and there is no obvious starting point for a newbie. But after finding and downloading the hardware and software support files, it is rather easy to build a system and install Linux if choosing the right FPGA development board. The Nios II The Nios II is a proprietary 32bit RISC architecture processor core developed by Altera for use in their FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by adding a predefined memory management unit and/or defining custom instructions and custom peripherals. EE Times-Asia eetasia.com Copyright 2013 emedia Asia Ltd. Page 4 of 5

5 Easy-to-use development environment No licence required for building a system when using the Quartus II Web Edition No extra JTAG programming tool needed Can only be used in Altera FPGAs Some IP cores have time-limited licences that will stop working after some time. They will continue to work as long as the development board is connected to your host computer. The Altera Quartus II and Nios II Embedded Design Suite make it very easy to build a NIOS II-based system and to write application software that will run on this system. The complete Nios II system is specified in the Qsys tool where the processor is configured and all other system components are added. Performance measurements The CoreMark benchmark C-programs were downloaded and installed for the different processors. The program suite was compiled using the GCC compiler that was part of the SDK installation. The results are as follows: To be totally honest, you should take these values "with a grain of salt," because the processors cores were implemented on different development boards and different GCC compiler versions were used. Conclusion I hope that this investigation will help you in deciding with soft-core processor to use. If you want to find out more, I would recommend that to build your own system using a similar setup as described in this article. Hands-on experience is worth much more than reading colourful sales brochures. About the author Sven-Ake Andersson is Senior ASIC/FPGA designer at Realtime Embedded. EE Times-Asia eetasia.com Copyright 2013 emedia Asia Ltd. Page 5 of 5