TEST REPORT SERIAL PERIPHERAL INTERFACE (SPI)

Transcription

1 CERN European Organization for Nuclear Research Beams Department Radio Frequency RF Feedbacks and Beam Control TEST REPORT SERIAL PERIPHERAL INTERFACE (SPI) By: Petri Leinonen BE-RF-FB Date: (Update )

2 TABLE OF CONTENTS 1. INTRODUCTION TEST SETUP Device under test (DUT) Measurement setup in the lab Communication setup SPI TESTS Experiment 1: SPI-bus operation Objective Test setup Test results Analysis of the results CONCLUSION... 13

3 3 1. INTRODUCTION This document describes the results of the Serial Peripheral Interface (SPI) bus tests of the version 1 of the FMC-DAC-4-CH-16bit-250MSPS mezzanine card; EDA The Digital-to-analog-converter, AD9747, is controlled via the SPI-bus and therefore the operation needs to be tested. The mezzanine cards provides four independent channels, each generating a sample and hold analogue voltage proportional to its 16 bit input digital word fed through the connector linking it to the carrier board. The on-board Digital-to-Analogue Converters generate a current which full scale value can be programmed via a Serial Peripheral Interface (SPI) between values ranging from 8.64mA to 31.7mA. After this stage an I-to-V-conversion is performed. The produced voltage is amplified and fed to a dual-position attenuator (typically 0dB and -18 db). The aim of this latter circuit is to extend the dynamic range of the output from 16 to 19 bits. When the digital signal has low amplitude, it is digitally amplified by 18 db and simultaneously attenuated by the same amount in the analogue domain. This result in more bits involved for the same output amplitude and thus more resolution. The signal is then further amplified and filtered to remove the sampling aliases. The sampling rate is from DC to 250 Ms/s. The mezzanine card is designed to be plugged on a carrier card which has a High Pin Count (HPC) FMC 400-pin connector and includes an FPGA where the mezzanine card data is being processed. This unit is foreseen to be used in a so-called beam control system, typically to generate a radio frequency (RF) modulated signal that feeds, after amplification, the accelerating cavities. In this latter context, the firmware block controlling this DAC board is called SDDS (Slave Direct Digital Synthesizer). Within the beam control system, the sampling clock is a high harmonic of the particles revolution frequency, provided by another FMC mezzanine board called Master Direct Digital Synthesizer or MDDS. This sampling rate value was chosen in order to ease the creation of the accelerating voltage which is also a harmonic of the revolution. 1 CERN Identification number for documents in EDMS(Equipment Data Management Service) EDA-02069:

4 4 2. TEST SETUP The test setup consists of three boards: a DAC mezzanine card, a transition board and a ML605 evaluation board. The ML605 provides the data processing (in a Virtex 6 FPGA) and the power via the transition board to the mezzanine. In addition, the ML605 evaluation kit provides various interfaces and connectors to be used with the external world. The transition board provides a clock signal for the DAC mezzanine card and it is used to change some voltage levels in order to be compliant with the 2.5V FPGA IOs.

5 Device under test (DUT) Figure 1. The mezzanine card hardware: a) the bottom side b) and the top side.

6 Measurement setup in the lab Figure 2. DUT, Transition board and ML605 evaluation kit test setup (from top to bottom) Communication setup The evaluation kit provides a test platform for the firmware and the daughter card hardware. At first, the communication channel was established between the daughter card and the ML605 board. The programming of the FPGA is done with the JTAG connection. After initializing the JTAG chain under Xilinx ISE, the FPGA was loaded with the firmware code. The communication itself happens through an UART-port. The data is sent from the computer and received by the evaluation kit, via a USB-cable, in serial format. The evolution kit has an USB-to-UART bridge on board which allows the data to be transferred via the USB port. The baud rate of the connection is 9600 bps. Python was used for programming the computer user interface. Python is a high-level object orientated language and it was selected to be the test interface with the evaluation kit. Python provides an open-source environment and easily readable code structure. In addition, it is a scripting language which makes it a powerful tool for hardware testing.

7 7 3. SPI TESTS 3.1. Experiment 1: SPI-bus operation Objective The aim of the SPI test is to verify the correct operation of the communication channel between the ML605 evaluation kit FPGA and the Digital-to-analog converter AD Test setup The SPI-bus was tested with a Python script by writing multiple sequences to the D/Aconverter and reading back the register contents from the chip. Oscilloscope (Tektronix DPO7254, 2.5GHz, 40Gs/s) was used to capture the data stream by probing the DAC IC s SPI pins. The data stream consists of three frames. A frame includes and instruction byte and four data bytes. After every frame the communication is stopped. SDO line is the output of the chip, SDIO is the input and SCLK is the clock line.

8 Test results Figure 3. SPI read after boot up gives default register contents, 0x01F9. Test report Serial Peripheral Interface (SPI) - Petri Leinonen BE-RF-FB

9 9 Figure 4. SPI write all zeros to the chip, 0x0000. Test report Serial Peripheral Interface (SPI) - Petri Leinonen BE-RF-FB

10 10 Figure 5. SPI readback all zeros after write, 0x0000. Test report Serial Peripheral Interface (SPI) - Petri Leinonen BE-RF-FB

11 11 Figure 6. SPI write, 0x0020, to the first two LSB registers. Test report Serial Peripheral Interface (SPI) - Petri Leinonen BE-RF-FB

12 12 Figure 7. SPI readback sequence, 0x0020, from LSB registers Analysis of the results SPI read and write operations work well with the SPI interface. Test report Serial Peripheral Interface (SPI) - Petri Leinonen BE-RF-FB

13 13 4. CONCLUSION The Serial Peripheral Interface bus was tested simply by writing sequences to the D/Aconverter chip and reading them back from the chip. A Python script was written for this test and the commands were sent through a serial link from the computer to the ML605 evaluation kit, and again via the transition board all the way to the mezzanine card. The same communication channel was used to receive the data from the mezzanine card to the PC. The tests reveal that the SPI-bus is working and no changes need to be performed to the second version of the hardware. Nevertheless, some Firmware changes are foreseen in order to improve the functionality.