Quasi-Static Scheduling of Embedded Software Using Free-Choice Petri Nets. Outline
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1 EE249: Design of Embedded Sysem (correcions) Quasi-Saic Scheduling of Embedded Sofware Using Free-Choice Peri Nes Marco Sgroi, Albero Sangiovanni-Vincenelli Universiy of California a Berkeley Luciano Lavagno Cadence Berkeley Labs Yosinori Waanabe Cadence European Labs EE249 - Fall Ouline Moivaion Scheduling Free-Choice Peri Nes Algorihm 2 1
2 EE249: Design of Embedded Sysem (correcions) Embedded Sofware Synhesis Sysem specificaion: se of concurren funcional blocks (DF acors, CFSMs, CSP, ) Sofware implemenaion: (smaller) se of concurren sofware asks Two sub-problems: Generae code for each ask (sofware synhesis) Schedule asks dynamically (dynamic scheduling) Goal: minimize real-ime scheduling overhead 3 Peri Nes Model 4 2
3 EE249: Design of Embedded Sysem (correcions) Peri Nes Model Schedule: 2, 3, 6... a = 5 c = a + b 5 Peri Nes Model Task 1 Task 2 Task 3 + RTOS Shared Processor 6 3
4 EE249: Design of Embedded Sysem (correcions) Classes of Scheduling Saic: schedule compleely deermined a compile ime Dynamic: schedule deermined a run-ime Quasi-Saic: mos of he schedule compued a compile ime, some scheduling decisions made a run-ime (bu only when necessary) 7 Embedded Sysems Specificaions Specificaion Scheduling Real-ime Conrol (preempion, suspension) Daa-dependen Conrol (if..hen..else, while..do) Daa Processing (+, -, *...) Dynamic Quasi-Saic Saic 8 4
5 EE249: Design of Embedded Sysem (correcions) An example Example: 2nd order IIR filer o(n) = k2 i(n) + k1 o(n-1) i k2 + o k1 Saic Daa Flow nework 9 Daa Processing IIR 2nd order filer o(n)=k1 o(n-1) + k2 i(n) i *k2 + o *k1 Schedule: i, *k2, *k1, +, o Schedule: i, *k1, *k2, +, o 10 5
6 EE249: Design of Embedded Sysem (correcions) Daa compuaion (Mulirae) Fas Fourier Transform Mulirae Daa Flow nework i FFT o i Peri Ne o Schedule: ii i FFT oo. o Sample rae conversion A B C D E 5 F Schedule: (147A) (147B) (98C) (28D) (32E) (160F) 11 Daa-dependen Conrol *2 i >0 o Schedule: i, if (i>0) hen{ /2} else{ *2}, o /2 Peri Nes provide a unified model for mixed conrol and daa processing specificaions Free-Choice (Equal Conflic) Nes: he oucome of a choice depends on he value of a oken (absraced non-deerminisically) raher han on is arrival ime 12 6
7 EE249: Design of Embedded Sysem (correcions) PNs and BDF >0 BDF nework F T F T Peri Ne 2 <=0 <=0 >0 > Swich/Selec vs. choice/merge PNs: No correlaion beween differen choices 13 PNs and BDF BDF nework Peri Ne >0 F F T F T PNs are no-deerminae 14 7
8 EE249: Design of Embedded Sysem (correcions) PNs and BDF BDF nework Peri Ne >0 TF F T F T PNs are no-deerminae 15 PNs and BDF BDF nework Peri Ne >0 F T TTF F T PNs are no-deerminae 16 8
9 EE249: Design of Embedded Sysem (correcions) Exising approaches Lee - Messerschmi 86 Saic Daa Flow: canno specify daa-dependen conrol Buck - Lee 94 Boolean Daa Flow: scheduling problem is undecidable Thoen - Goossens - De Man 96 Even graph: no schedulabiliy check, no minimizaion of number of asks Lin 97 Safe Peri Ne: no schedulabiliy check, no muli-rae Thiele - Teich 99 Bounded Peri Ne: parial schedulabiliy check, complex (reachabiliy-based) algorihm 17 Scheduling Peri Nes Peri Nes provide a unified model for mixed conrol and daaflow specificaion Mos properies are decidable A lo of heory available Absrac Daaflow neworks by represening if-hen-else srucures as non-deerminisic choices Non-deerminisic acors (choice and merge) make he nework non-deerminae according o Kahn s definiion Free-Choice: he oucome of a choice depends on he value of a oken (absraced non-deerminisically) raher han on is arrival ime 18 9
10 EE249: Design of Embedded Sysem (correcions) Bounded scheduling (Marked Graphs) A finie complee cycle is a finie sequence of ransiion firings ha reurns he ne o is iniial sae Bounded memory Infinie execuion To find a finie complee cycle solve f(s) D = D = T-invarian f(s) = (4,2,1) 2 No schedule f(s) D = 0 has no soluion Bounded scheduling (Marked Graphs) Exisence of a T-invarian is only a necessary condiion Verify ha he ne does no deadlock by simulaing he minimal T-invarian [Lee87] T-invarian f(σ) = (4,2,1) 224 (0,0) (0,0) s = 224 T-invarian f(σ) = (3,2,1) No enough iniial okens Deadlock 20 10
11 EE249: Design of Embedded Sysem (correcions) Free-Choice Peri Nes (FCPN) Marked Graph (MG) Free-Choice Free-Choice: choice depends on oken value raher han arrival ime easy o analyze (using srucural mehods) Confusion (no-free-choice) 21 Bounded scheduling (Free-Choice Peri Nes) Can he adversary ever force oken overflow?
12 EE249: Design of Embedded Sysem (correcions) Bounded scheduling (Free-Choice Peri Nes) Can he adversary ever force oken overflow? Bounded scheduling (Free-Choice Peri Nes) Can he adversary ever force oken overflow?
13 EE249: Design of Embedded Sysem (correcions) Bounded scheduling (Free-Choice Peri Nes) Can he adversary ever force oken overflow? Bounded scheduling (Free-Choice Peri Nes) Can he adversary ever force oken overflow?
14 EE249: Design of Embedded Sysem (correcions) Schedulabiliy (FCPN) Quasi-Saic Scheduling a compile ime find one schedule for every condiional branch a run-ime choose one of hese schedules according o he acual value of he daa. Σ={( 2 4),( 3 5)} 27 Bounded scheduling (Free-Choice Peri Nes) Valid schedule S is a se of finie firing sequences ha reurn he ne o is iniial sae conains one firing sequence for every combinaion of oucomes of he free choices ( 2 4) ( 3 5) S={( 2 4),( 3 5)} 3 Schedulable
15 EE249: Design of Embedded Sysem (correcions) How o check schedulabiliy Basic inuiion: every resoluion of daadependen choices mus be schedulable Algorihm: Decompose (by applying he Reducion Algorihm) he given Equal Conflic Ne ino as many Conflic-Free componens as he number of possible resoluions of he non-deerminisic choices. Check if every componen is saically schedulable Derive a valid schedule, i.e. a se of finie complee cycles one for each conflic-free componen 29 Allocaabiliy (Hack, Teruel) An Allocaion is a conrol funcion ha chooses which ransiion fires among several conflicing ones ( A: P T). A Reducion is he Conflic Free Ne generaed from one Allocaion by applying he Reducion Algorihm. A ECN is allocaable if every Reducion generaed from an allocaion is consisen. Theorem: A ECN is schedulable iff i is allocaable and every Reducion is schedulable (following Lee) 30 15
16 EE249: Design of Embedded Sysem (correcions) Reducion Algorihm T-allocaion A1={,2,4,5,6,7} How o find a valid schedule 2 4 Conflic Relaion Ses:{2,3},{7,8} T-allocaions: A1={,2,4,5,6,7,9,0} A2={,3,4,5,6,7,9,0} A3={,2,4,5,6,8,9,0} 6 A4={,3,4,5,6,8,9,0}
17 EE249: Design of Embedded Sysem (correcions) Valid schedule ( ) ( ) ( ) ( ) Σ= C code implemenaion 6 p1 p p2 4 2 p4 5 Σ={( ) ( )} Task 1: { ; if (p1) hen{ 2; coun(p2)++; if (coun(p2) = 2) hen{ 4; } else{ 3; 5;} } Task 2: { 6; 7; 5; } coun(p2) = coun(p2) - 2;} 34 17
18 EE249: Design of Embedded Sysem (correcions) Applicaion example: ATM Swich Incoming cells (non-periodic) Inpu cells: accep? Inernal buffer Oupu cells: emi? Clock (periodic) No saic schedule due o: Inpus wih independen raes (need Real-Time dynamic scheduling) Daa-dependen conrol (can use Quasi-Saic Scheduling) Ougoing cells 35 Peri Nes Model 36 18
19 EE249: Design of Embedded Sysem (correcions) Funcional decomposiion Accep/discard cell 4 Tasks Oupu ime selecor Clock divider Oupu cell enabler 37 Decomposiion wih min # of asks Inpu cell processing 2 Tasks Oupu cell processing 38 19
20 EE249: Design of Embedded Sysem (correcions) Real-ime scheduling of independen asks Task 1 Task 2 + RTOS Shared Processor 39 ATM: experimenal resuls Funcional pariioning (4+1 asks) QSS (2 asks) Sw Implemenaion QSS Funcional pariioning Number of asks 2 5 Lines of C code Clock cycles
21 EE249: Design of Embedded Sysem (correcions) Conclusion Advanages of Quasi-Saic Scheduling: QSS minimizes run-ime overhead wih respec o Dynamic Scheduling by Auomaic pariioning of he sysem funcions ino a minimum number of concurren asks The underlying model is FCPN: can check schedulabiliy before code generaion Fuure work Larger PN classes Code opimizaions 41 21
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