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1 P-CHANNEL 60V Ω - 16A D2PAK STripFET MOSFET Table 1: General Features TYPE V DSS R DS(on) I D Pw Figure 1: Package STB16PF06L 60 V < Ω 16 A 70 W TYPICAL R DS (on) = 0.11 Ω LOW THRESHOLD DEVICE LOW GATE CHARGE DESCRIPTION This MOSFET is the latest development of STMicroelectronics unique Single Feature Size strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalance characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS MOTOR CONTROL DC-DC CONVERTERS Table 2: Order Codes D 2 PAK TO-263 Figure 2: Internal Schematic Diagram PART NUMBER MARKING PACKAGE PACKAGING STB16PF06LT4 B16PF06L D 2 PAK TAPE & REEL 1 3 Rev. 1 September /10

2 Table 3: Absolute Maximum ratings Symbol Parameter Value Unit V DS Drain-source Voltage (V GS = 0) 60 V V DGR Drain-gate Voltage (R GS = 20 kω) 60 V V GS Gate-source Voltage ± 16 V I D Drain Current (continuous) at T C = 25 C 16 A I D Drain Current (continuous) at T C = 100 C 11.4 A I DM ( ) Drain Current (pulsed) 64 A P TOT Total Dissipation at T C = 25 C 70 W Derating Factor 0.4 W/ C dv/dt (1) Peak Diode Recovery voltage slope 20 V/ns E AS (2) Single Pulse Avalanche Energy 250 mj T j Operating Junction Temperature Storage Temperature - 55 to 175 C T stg ( ) Pulse width limited by safe operating area (1) I SD 16A, di/dt 100A/µs, V DD V (BR)DSS, T j T JMAX. (2) Starting T j = 25 C, I D = 8 A, V DD = 30 V Note:For the P-CHANNEL MOSFET actual polarity of voltages and current has to be reverse Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Max 2.14 C/W Rthj-PCB(#) Thermal Resistance Junction-PCB Max 34 C/W T l Maximum Lead Temperature For Soldering 300 C Purpose (1.6 mm frrom case, for 10sec) (#) When Mounted on 1 inch 2 FR-4 board, 2 oz of Cu ELECTRICAL CHARACTERISTICS (T CASE =25 C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol Parameter Test Conditions Min. Typ. Max. Unit V (BR)DSS Drain-source I D = 250µA, V GS = 0 60 V Breakdown Voltage I DSS Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating V DS = Max Rating, T C = 125 C 1 10 µa µa I GSS Gate-body Leakage V GS = ± 16V ±100 na Current (V DS = 0) V GS(th) Gate Threshold Voltage V DS = V GS, I D = 100µA 1.5 V R DS(on) Static Drain-source On Resistance V GS = 10V, I D = 8 A V GS = 5V, I D = 8 A Ω Ω 2/10

3 ELECTRICAL CHARACTERISTICS (CONTINUED) Table 6: Dynamic Symbol Parameter Test Conditions Min. Typ. Max. Unit g fs Forward Transconductance V DS = 10 V, I D =3 A 7.2 S C iss C oss C rss t d(on) t r t d(off) t f Q g Q gs Q gd Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Table 7: Source Drain Diode Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. V DS = 25V, f = 1 MHz, V GS = V DD = 30 V, I D = 8 A, R G = 4.7Ω V GS = 4.5 V (Resistive Load, Figure 1) V DD = 48 V, I D = 16 A, V GS = 4.5V (See test circuit, Figure 2) pf pf pf ns ns ns ns 15.5 nc nc nc Symbol Parameter Test Conditions Min. Typ. Max. Unit I SD I SDM (2) Source-drain Current Source-drain Current (pulsed) A A V SD (1) Forward On Voltage I SD = 8 A, V GS = V t rr Q rr I RRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 16 A, di/dt = 100A/µs V DD = 20V, T j = 150 C (see test circuit, Figure 3) ns nc A 3/10

4 Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 5: Transconductance Figure 7: Transfer Characteristics Figure 8: Static Drain-source On Resistance 4/10

5 Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 11: Dource-Drain Diode Forward Characteristics Figure 13: Normalized On Resistance vs Temperature Figure 14: Normalized Breakdown Voltage vs Temperature 5/10

6 Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform Figure 16: Switching Times Test Circuit For Resistive Load Figure 17: Test Circuit For Inductive Load Switching and Diode Recovery Times Figure 19: Gate Charge Test Circuit 6/10

7 3 STB16PF06L D 2 PAK MECHANICAL DATA TO-247 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A A A B B C C D D E E G L L L M R V2 0º 4º 1 7/10

8 D 2 PAK FOOTPRINT TUBE SHIPMENT (no suffix)* DIM. TAPE MECHANICAL DATA mm TAPE AND REEL SHIPMENT (suffix T4 )* inch MIN. MAX. MIN. MAX. A B D D E F K P P P R T W * on sales type DIM. REEL MECHANICAL DATA mm inch MIN. MAX. MIN. MAX. A B C D G N T BASE QTY BULK QTY /10

9 Table 8: Revision History Date Revision Description of Changes 13/Sep/ First Release. 9/10

10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 10/10

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