A simple example: 1-bit binary adder

Transcription

1 Realizing oolean logic lgebraic expressions to gates Mapping between different gates Discrete logic gate components (used in lab 1) Spring 2010 CSE370 - III - Realizing oolean Logic 1 simple example: 1-bit binary adder Cout Cin Inputs:,, Carry-in Outputs: Sum, Carry-out S S S S S Cin Cout S S Cout Cin S = Cin + Cin + Cin + Cin Cout = Cin + Cin + Cin + Cin Spring 2010 CSE370 - III - Realizing oolean Logic 2

2 pply the theorems to simplify expressions The theorems of oolean algebra can simplify expressions e.g., full adder s carry-out function Cout = Cin + Cin + Cin + Cin = Cin + Cin + Cin + Cin + Cin = Cin + Cin + Cin + Cin + Cin = ( + ) Cin + Cin + Cin + Cin = (1) Cin + Cin + Cin + Cin = Cin + Cin + Cin + Cin + Cin = Cin + Cin + Cin + Cin + Cin = Cin + ( + ) Cin + Cin + Cin = Cin + (1) Cin + Cin + Cin = Cin + Cin + (Cin + Cin) = Cin + Cin + (1) = Cin + Cin + adding extra terms creates new factoring opportunities Spring 2010 CSE370 - III - Realizing oolean Logic 3 simple example: 1-bit binary adder Cout Cin Inputs:,, Carry-in Outputs: Sum, Carry-out S S S S S Cin Cout S Cin Cout = Cin + Cin + S Cout S = Cin + Cin + Cin + Cin = ( Cin + Cin ) + ( Cin + Cin ) = + = xor = xor ( xor Cin) Spring 2010 CSE370 - III - Realizing oolean Logic 4

3 From oolean expressions to logic gates NOT ~ / ND OR Spring 2010 CSE370 - III - Realizing oolean Logic 5 From oolean expressions to logic gates (cont d) NND OR xor = + or but not both ("inequality", "difference") = xnor = + and are the same ("equality", "coincidence") Spring 2010 CSE370 - III - Realizing oolean Logic 6

4 Full adder: Carry-out efore oolean minimization Cout = 'Cin + 'Cin + Cin' + Cin fter oolean minimization Cout = Cin + Cin + Spring 2010 CSE370 - III - Realizing oolean Logic 7 Full adder: Sum efore oolean minimization Sum = ''Cin + 'Cin' + 'Cin' + Cin fter oolean minimization Sum = ( ) Cin Spring 2010 CSE370 - III - Realizing oolean Logic 8

5 Preview: 2-bit ripple-carry adder 1-it dder C in C out C in C out C in C out Sum 1 Sum 2 Sum Spring 2010 CSE370 - III - Realizing oolean Logic 9 Mapping truth tables to logic gates Given a truth table: 1. Write the oolean expression 2. Minimize the oolean expression 3. Draw as gates 4. Map to available gates 1 C F F = C + C+ C+C = (C +C)+C( +) = +C 3 4 Spring 2010 CSE370 - III - Realizing oolean Logic 10

6 Conversion between gate types Example: map ND/OR network to -only network C D C D \ \ \C \D conserve "bubbles" conserve "bubbles" Spring 2010 CSE370 - III - Realizing oolean Logic 11 Conversion between gate types (cont d) Example: verify equivalence of two forms C D \ \ \C \D = { [ ( + ) + (C + D ) ] } = { ( + ) (C + D ) } = ( + ) + (C + D ) = ( ) + (C D) Spring 2010 CSE370 - III - Realizing oolean Logic 12

7 ctivity: convert to NND gates Spring 2010 CSE370 - III - Realizing oolean Logic 13 Example: tally circuit (outputs # of 1s in inputs) T2 T T1 = = ( ) 3 + ( ) 3 = (1 xor 2) 3 + (1 xor 2) 3 = (1 xor 2) xor 3 T2 = = 1 (2 3) + 1 (2 + 3) Spring 2010 CSE370 - III - Realizing oolean Logic 14

8 From oolean expressions to logic gates More than one way to map expressions to gates e.g., = (C + D) = ( ( (C + D))) use of 3-input gate Spring 2010 CSE370 - III - Realizing oolean Logic 15 Waveform view of logic functions Just a sideways truth table but note how edges don t line up exactly it takes time for a gate to switch its output! time change in takes time to "propagate" through gates Spring 2010 CSE370 - III - Realizing oolean Logic 16

9 Choosing different realizations of a function C two-level realization (we don t count NOT gates) multi-level realization (gates with fewer inputs) OR gate (easier to draw but costlier to build) Spring 2010 CSE370 - III - Realizing oolean Logic 17 re all realizations equivalent? Under the same input stimuli, the three alternative implementations have almost the same waveform behavior delays are different glitches (hazards) may arise these could be bad, it depends variations due to differences in number of gate levels and structure The three implementations are functionally equivalent Spring 2010 CSE370 - III - Realizing oolean Logic 18

10 Which realization is best? Reduce number of inputs literal: input variable (complemented or not) can approximate cost of logic gate as 2 transistors per literal why not count inverters? fewer literals means less transistors smaller circuits fewer inputs implies faster gates gates are smaller and thus also faster fan-ins (# of gate inputs) are limited in some technologies the programmable logic we ll be using later in the quarter Reduce number of gates fewer gates (and the packages they come in) means smaller circuits directly influences manufacturing costs Spring 2010 CSE370 - III - Realizing oolean Logic 19 Which realization is best? (cont d) Reduce number of levels of gates fewer level of gates implies reduced signal propagation delays minimum delay configuration typically requires more gates wider, less deep circuits Hazards/glitches one without hazards may be preferable/necessary How do we explore tradeoffs between increased circuit delay and size? automated tools to generate different solutions logic minimization: reduce number of gates and complexity logic optimization: reduction while trading off against delay Spring 2010 CSE370 - III - Realizing oolean Logic 20

11 Random logic gates Transistors quickly integrated into logic gates (1960s) Catalog of common gates (1970s) Texas Instruments Logic Data ook the yellow bible all common packages listed and characterized (delays, power) typical packages: in 14-pin IC: 6-inverters, 4 NND gates, 4 OR gates Today, very few of these parts are still in use However, parts libraries exist for chip design designers reuse already characterized logic gates on chips same reasons as before difference is that the parts don t exist in physical inventory created as needed Spring 2010 CSE370 - III - Realizing oolean Logic 21 Some logic gate components Quad 2-input NNDs 00 Quad 2-input s 02 6 inverters (NOTs) input NNDs 10 Spring 2010 CSE370 - III - Realizing oolean Logic 22