The MOS Transistor. Debdeep Mukhopadhyay IIT Madras

Transcription

1 The MOS Transistor Debdeep Mukhopadhyay IIT Madras

2 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C ( V/ t) -> t = (C/I) V Capacitance and current determine speed Also explore what a degraded level really means

3 MOS Characteristics MOS majority carrier device Carriers: e -- in nmos, holes in pmos V t channel threshold voltage (cuts off for voltages < V t )

4 nmos Enhancement Transistor Moderately doped p type Si substrate 2 Heavily doped n + regions

5 I vs. V Plots Enhancement and depletion transistors CMOS uses only enhancement transistors nmos uses both

6 Materials and Dopants SiO 2 low loss, high dielectric strength High gate fields are possible n type impurities: P, As, Sb p type impurities: B, Al, Ga, In

7 Bipolar vs. MOS Bipolar p-n junction metallurgical MOS Inversion layer / substrate junction field-induced Voltage-controlled switch, conducts when V gs V t e -- swept along channel when V ds > 0 by horizontal component of E Pinch-off conduction by e - drift mechanism caused by positive drain voltage Pinched-off channel voltage: V gs V t (saturated) Reverse-biased p-n junction insulates from the substrate

8 MOSFET Transistors MOSFET For given V ds & V gs, I ds controlled by: Distance between source & drain L Channel width W Threshold VoltageV t Gate oxide thickness t ox dielectric constant of gate oxide ε Carrier mobility µ

9 MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion (a) V g < polysilicon gate silicon dioxide insulator p-type body 0 < V g < V t depletion region + - (b) V g > V t + - inversion region depletion region (c)

10 Terminal Voltages Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V ds = V d V s = V gs -V gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation V s V gs V g + V ds + V gd - V d

11 nmos Cutoff No channel I ds = 0 V gs = g + - V gd s d n+ n+ p-type body b

12 nmos Linear Channel forms Current flows from d to s e - from s to d I ds increases with V ds Similar to linear resistor At drain end of channel, only difference between gate & drain voltages effective for channel creation V gs > V t V gs > V t V gd = V gs n+ n+ V ds = 0 p-type body b + - s s g g + - V gs > V gd > V t n+ n+ 0 < V ds < V gs -V t p-type body b d d I ds

13 nmos Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source V gs > V t + - g + - V gd < V t s d I ds n+ n+ V ds > V gs -V t p-type body b

14 I-V Characteristics In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving?

15 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = gate t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain - - channel n+ - + n+ V s V ds p-type body V d

16 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) gate V g + + source V gs C g V gd drain - - channel n+ - + n+ V s V ds p-type body V d

17 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL V = t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) gate V g + + source V gs C g V gd drain - - channel n+ - + n+ V s C ox = ε ox / t ox V ds p-type body V d

18 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL V = V gc V t = (V gs V ds /2) V t t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) gate V g + + source V gs C g V gd drain - - channel n+ - + n+ V s C ox = ε ox / t ox V ds p-type body V d

19 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E- field between source and drain v =

20 Carrier Velocity Charge is carried by e- Carrier velocity v proportional to lateral E- field between source and drain v = µe µ called mobility E =

21 Carrier Velocity Charge is carried by e- Carrier velocity v proportional to lateral E- field between source and drain v = µe µ called mobility E = V ds /L Time for carrier to cross channel: t =

22 Carrier Velocity Charge is carried by e- Carrier velocity v proportional to lateral E- field between source and drain v = µe µ called mobility E = V ds /L Time for carrier to cross channel: t = L / v

23 nmos Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I = ds

24 nmos Linear I-V Now we know I How much charge Q channel is in the channel How much time t each carrier takes to cross ds = = Q channel t

25 nmos Linear I-V Now we know I How much charge Q channel is in the channel How much time t each carrier takes to cross ds Qchannel = t W V = µ C V V V L V = β V ds gs V t V 2 ds ds ox gs t 2 ds W β = µcox L

26 nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current I = ds

27 nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I = β V V dsat V 2 ds gs t dsat

28 nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I = β V V dsat V 2 β = ( V ) 2 gs Vt 2 ds gs t dsat

29 nmos I-V Summary Shockley transistor models 0 Vgs < V V I = β V V ds V V V 2 < β ( V V ) 2 V > V 2 ds gs t ds ds dsat Note the dependencies on W, L gs t ds dsat t cutoff linear saturation W Cgµ ins 0 WL β = K, K =, Cg = L WL D

30 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change

31 MOS as switch MOS can be viewed as switches. The switches are electrically controlled.

32 NMOS as a switch Vin=Vdd Vin=0 Gate=Vdd Vgs Vout I Load Capacitor Ground Gate=Vdd Vgs Vout=Vdd I Load Capacitor Ground Assume capacitor (C L ) is initially discharged Gate=1, Vin=1 C L begins to conduct and charges toward 1 (Vdd) and stops at (Vdd-Vt) Signal is degraded Gate=1, Vin=0 C L begins to discharge toward 0 Good passer of 0.

33 CMOS Signal Transfer Property Source Gate Drain Gate 0 1 Path Closed Open Transmits 1 well Transmits 0 poorly pmos Drain Gate Source nmos Gate 0 1 Path Open Closed Transmits 0 well Transmits 1 poorly

34 CMOS Transmission Gate Transmit signal from INPUT to OUTPUT when Gate is closed Gate (complementary of Gate) Gate pmos nmos OUTPUT INPUT Source Drain OUTPUT 0 1 OFF ON OFF ON Z INPUT Gate Z : High-Impedance State, consider the terminal is floating

35 CMOS Inverter Vcc Vin Combines the best of both.

36 nmos Operation Cutoff V gsn < Linear V gsn > Saturated V gsn > V dsn < V dsn > V DD I dsp V in V out I dsn

37 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V DD V in I dsp I dsn V out

38 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V gsn = V in V DD V dsn = V out V in I dsp V out I dsn

39 nmos Operation Cutoff V gsn < V tn V in < V tn Linear V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in -V tn Saturated V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in -V tn V gsn = V in V DD V dsn = V out V in I dsp V out I dsn

40 pmos Operation Cutoff V gsp > Linear V gsp < V dsp > Saturated V gsp < V dsp < V DD V in I dsp I dsn V out

41 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V DD V in I dsp I dsn V out

42 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V DD V gsp = V in -V DD V tp < 0 V dsp = V out -V DD V in I dsp I dsn V out

43 pmos Operation Cutoff V gsp > V tp V in > V DD + V tp Linear V gsp < V tp V in < V DD + V tp V dsp > V gsp V tp V out > V in -V tp Saturated V gsp < V tp V in < V DD + V tp V dsp < V gsp V tp V out < V in -V tp V DD V gsp = V in -V DD V tp < 0 V dsp = V out -V DD V in I dsp I dsn V out

44 CMOS Inverter Voltage Transfer Characteristic V out NMOS off PMOS lin NMOS sat PMOS lin NMOS sat PMOS sat NMOS lin PMOS sat NMOS lin PMOS off V in

45 3 INPUT CMOS NAND GATE PULL UP NETWORK A B C PULL DOWN NETWORK Y=~ABC

46 Key Points There is always a path from VDD or GND to the output. There is no path from the VDD to GND (for our purpose). Thus this gate has a very low power consumption. Fully restored logic (why?)

47 Complex CMOS gates Design F=ab+bc+ac Design the complementary logic

48 Exercises Design an AND OR Inverter gate:

49 Tristate Inverter EN Inp Out Z Z 1 0 What will be the CMOS level circuit for the above?

50 Tristate Inverter