MOS Transistor Theory
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1 MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 James Morizio 1
2 EE 261 James Morizio 2
3 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C ( V/ t) -> t = (C/I) V Capacitance and current determine speed Also explore what a degraded level really means EE 261 James Morizio 3
4 MOS Transistor Theory Study conducting channel between source and drain Modulated by voltage applied to the gate (voltagecontrolled device) nmos transistor: majority carriers are electrons (greater mobility), p-substrate doped (positively doped) pmos transistor: majority carriers are holes (less mobility), n-substrate (negatively doped) EE 261 James Morizio 4
5 Terminal Voltages Mode of operation depends on V g, V d, V s + + V gs = V g V V gs s - V gd = V g V d V V ds = V d V s = V gs - V s - gd V + ds Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation V g V gd - V d EE 261 James Morizio 5
6 Gate Biasing Source Gate SiO 2 Drain n + Channel n E V gs =0: no current flows from source to drain (insulated by two reverse biased pn junctions p-substrate V gs >0: electric field created across substrate V SS (Gnd) Electrons accumulate under gate: region changes from p-type to n-type Conduction path between source and drain EE 261 James Morizio 6
7 p-substrate nmos Device Behavior Polysilicon gate Oxide insulator Inversion Region (n-type) Depletion region Depletion region V gs << V t Accumulation mode V gs = V t Depletion mode V gs > V t Inversion mode Enhancement-mode transistor: Conducts when gate bias V gs > V t Depletion-mode transistor: Conducts when gate bias is zero EE 261 James Morizio 7
8 nmos Cutoff No channel I ds = 0 V gs = g + - V gd s d n+ n+ p-type body b EE 261 James Morizio 8
9 nmos Linear Channel forms Current flows from d to s e - from s to d I ds increases with V ds Similar to linear resistor V gs > V t + - s g + - V gd = V gs n+ n+ V ds = 0 p-type body b d V gs > V t + - g + - V gs > V gd > V t s d I ds n+ n+ p-type body b 0 < V ds < V gs -V t EE 261 James Morizio 9
10 nmos Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source V gs > V t + - g + - V gd < V t s d I ds n+ n+ V ds > V gs -V t p-type body b EE 261 James Morizio 10
11 I-V Characteristics In linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? EE 261 James Morizio 11
12 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = gate t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain - - channel n+ - + n+ V s V ds p-type body V d EE 261 James Morizio 12
13 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) gate V g + + source V gs C g V gd drain - - channel n+ - + n+ V s V ds p-type body V d EE 261 James Morizio 13
14 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL V = t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) gate V g + + source V gs C g V gd drain - - channel n+ - + n+ V s C ox = ε ox / t ox V ds p-type body V d EE 261 James Morizio 14
15 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL V = V gc V t = (V gs V ds /2) V t C ox = ε ox / t ox gate t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain - - channel n+ - + n+ V s V ds p-type body V d EE 261 James Morizio 15
16 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = EE 261 James Morizio 16
17 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = µe E = µ called mobility EE 261 James Morizio 17
18 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = µe E = V ds /L µ called mobility Time for carrier to cross channel: t = EE 261 James Morizio 18
19 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = µe E = V ds /L µ called mobility Time for carrier to cross channel: t = L / v EE 261 James Morizio 19
20 nmos Linear I-V Now we know I = ds How much charge Q channel is in the channel How much time t each carrier takes to cross EE 261 James Morizio 20
21 nmos Linear I-V Now we know I ds How much charge Q channel is in the channel How much time t each carrier takes to cross = = Q channel t EE 261 James Morizio 21
22 nmos Linear I-V Now we know I ds How much charge Q channel is in the channel How much time t each carrier takes to cross Qchannel = t W V = µ C V V V L V = β V ds gs V t V 2 ds ds ox gs t 2 ds = W β µcox L EE 261 James Morizio 22
23 nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current I ds = EE 261 James Morizio 23
24 nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I = β V V dsat V 2 ds gs t dsat EE 261 James Morizio 24
25 nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I dsat ds = β Vgs V t V 2 dsat β = ( V ) 2 gs Vt 2 EE 261 James Morizio 25
26 nmos I-V Summary Shockley 1 st order transistor models 0 Vgs < V V I = β V V ds V V V 2 < β ( V V ) 2 V > V 2 ds gs t ds ds dsat gs t ds dsat t cutoff linear saturation EE 261 James Morizio 26
27 Current-Voltage Relations EE 261 James Morizio 27
28 Current-Voltage Relations k n : transconductance of transistor W : width-to-length ratio L As W increases, more carriers available to conduct current As L increases, V ds diminishes in effect (more voltage drop). Takes longer to push carriers across the transistor, reducing current flow EE 261 James Morizio 28
29 For a 0.6 µm process From AMI Semiconductor t ox = 100 Å µ = 350 cm 2 /V*s V t = 0.7 V Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 λ Example 14 W W W β = µ Cox = ( 350) 120 µ A/ V 8 = L L L I ds (ma) V ds V gs = 5 V gs = 4 V gs = 3 V gs = 2 V gs = 1 EE 261 James Morizio 29
30 pmos I-V All dopings and voltages are inverted for pmos Mobility µ p is determined by holes Typically 2-3x lower than that of electrons µ n 120 cm 2 /V*s in AMI 0.6 µm process Thus pmos must be wider to provide same current In this class, assume µ n / µ p = 2 to 3 EE 261 James Morizio 30
31 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion EE 261 James Morizio 31
32 Gate Capacitance Approximate channel as connected to source C gs = ε ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 ff/µm polysilicon gate W t ox L n+ n+ p-type body SiO2 gate oxide (good insulator, ε ox = 3.9ε 0 ) EE 261 James Morizio 32
33 The Gate Capacitance EE 261 James Morizio 33
34 Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted Varies with process EE 261 James Morizio 34
35 Diffusion Capacitance EE 261 James Morizio 35
36 Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S R S R D D W Drain R S = (L S /W)R + R C R D = (L D /W)R + R C R C : contact resistance R : sheet resistance per square of drain-source diffusion EE 261 James Morizio 36
37 Body Effect Many MOS devices on a common substrate Substrate voltage of all devices are normally equal But several devices may be connected in series Increase in source-to-substrate voltage as we proceed vertically along the chain V 12 g2 g1 V11 d2 s2 d1 s1 V sb2 = 0 V sb1 = 0 Net effect: slight increase in threshold voltage V t, V t2 >V t1 EE 261 James Morizio 37
38 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing EE 261 James Morizio 38
39 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V g = If V s > -V t, V gs < V t Hence transistor would turn itself off nmos pass transistors pull no higher than -V tn Called a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than V tp EE 261 James Morizio 39
40 Pass Transistor Ckts V SS EE 261 James Morizio 40
41 Pass Transistor Ckts Vs = -V tn VDD -Vtn VDD-Vtn -V tn V s = V tp -V tn -2V tn V SS EE 261 James Morizio 41
42 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay EE 261 James Morizio 42
43 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g d R/k kc s kc kc g d k s g s kc 2R/k kc kc d EE 261 James Morizio 43
44 RC Values Capacitance C = C g = C s = C d = 2 ff/µm of gate width Values similar across many processes Resistance R 6 KΩ in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 λ) Or maybe 1 µm wide device Doesn t matter as long as you are consistent EE 261 James Morizio 44
45 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change EE 261 James Morizio 45
46 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change EE 261 James Morizio 46
47 DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 -> V out = When V in = -> V out = 0 In between, V out depends on transistor size and current V in I dsp V out By KCL, must settle such that I dsn I dsn = I dsp We could solve equations But graphical solution gives more insight EE 261 James Morizio 47
48 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation? EE 261 James Morizio 48
49 nmos Operation Cutoff V gsn < Linear V gsn > V dsn < Saturated V gsn > V dsn > V in I dsp I dsn V out EE 261 James Morizio 49
50 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V in I dsp I dsn V out EE 261 James Morizio 50
51 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V gsn = V in I dsp V dsn = V out V in I dsn V out EE 261 James Morizio 51
52 nmos Operation Cutoff V gsn < V tn V in < V tn Linear V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in - V tn Saturated V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in - V tn V gsn = V in I dsp V dsn = V out V in I dsn V out EE 261 James Morizio 52
53 pmos Operation Cutoff V gsp > Linear V gsp < V dsp > Saturated V gsp < V dsp < V in I dsp I dsn V out EE 261 James Morizio 53
54 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V in I dsp I dsn V out EE 261 James Morizio 54
55 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V gsp = V in - V tp < 0 V dsp = V out - V in I dsp I dsn V out EE 261 James Morizio 55
56 pmos Operation Cutoff V gsp > V tp V in > + V tp Linear V gsp < V tp V in < + V tp V dsp > V gsp V tp V out > V in - V tp Saturated V gsp < V tp V in < + V tp V dsp < V gsp V tp V out < V in - V tp V gsp = V in - V tp < 0 V dsp = V out - V in I dsp I dsn V out EE 261 James Morizio 56
57 I-V Characteristics Make pmos wider than nmos such that β n = β p V gsn5 I dsn V gsn4 V gsn3 -V dsp V gsp1 V gsp2-0 V gsn2 V gsn1 V gsp3 V dsn V gsp4 -I dsp V gsp5 EE 261 James Morizio 57
58 A B DC Transfer Curve Transcribe points onto V in vs. V out plot V out C 0 D E V tn /2 +V tp V in EE 261 James Morizio 58
59 Operating Regions Revisit transistor operating regions Region A B C D E nmos pmos V out A B 0 C D E V tn /2 +V tp V in EE 261 James Morizio 59
60 Operating Regions Revisit transistor operating regions Region nmos pmos A B A Cutoff Linear B C Saturation Saturation Linear Saturation V out C D E Linear Linear Saturation Cutoff 0 D E V tn /2 +V tp V in EE 261 James Morizio 60
61 Beta Ratio If β p / β n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent inverter V out β p 0.1 β = n β p 10 β = n V in EE 261 James Morizio 61
62 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range EE 261 James Morizio 62
63 Logic Levels To maximize noise margins, select logic levels at V out β p /β n > 1 V in V out 0 V in EE 261 James Morizio 63
64 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic V out Unity Gain Points Slope = -1 V OH β p /β n > 1 V in V out V OL 0 V tn V IL V IH - V tp V in EE 261 James Morizio 64
65 EE 261 James Morizio 65
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