The Impact of NAND Lithography Trends on System Design

Transcription

1 The Impact of NAND Lithography Trends on System Design Michael Abraham NAND and Emerging Memory Architect Micron Technology, Inc. August

2 Abstract NAND Flash is quickly moving to sub-20nm and 3D lithographies, making it the fastest scaling semiconductor technology ever This talk covers the impact that these shrinks have to NAND s architecture, performance, and reliability Prepare for these changes and to learn to counteract some of them through improved system design August

3 40 NAND Process Migration: A Lithography Race to the Bottom Process Node (nm) nm Class 25nm Class 10 Q4-08 Q1-09 Q2-09 Q3-09 Q4-09 Q1-10 Q2-10 Q3-10 Q4-10 Q1-11 Q2-11 Q3-11 Q4-11 Q1-12 Q2-12 Q3-12 Q4-12 Q1-13 Q2-13 Q3-13 Q4-13 Volume Production Dates 20nm Class 10nm Class Company A Company B Company C Company D August Data based on publicly available information

4 NAND Die Densities Continue to Grow As lithographies shrink, there is significant pressure to achieve lower costs per bit while maintaining or improving system performance For a given process node, the lowest cost per bit comes from increasing the total number of bits per die (e.g. the die density) NAND Flash TAM by Density (Units) 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% Gb (32GB) 128Gb (16GB) 64Gb (8GB) 32Gb (4GB) 16Gb (2GB) 8Gb (1GB) Source: isuppli 1Q13 August Gb 2Gb 1Gb 512Mb 256Mb 128Mb

5 Memory Organization Trends NAND block sizes continue to increase Though the number of erasable blocks per die remains stable at ~2,048 blocks per die, block sizes are increasing Larger page sizes and more planes increase sequential throughput For a given litho node, increasing the number of pages per block reduces the die size and therefore the cost per bit Block size (B) Data Bytes per Operation Pages per Block August

6 Larger Page Sizes Improve Sequential Write Performance For a fixed page size across process nodes, write throughput decreases as the NAND process shrinks NAND vendors increase the page size to compensate for slowing array performance Write throughput decreases with more bits per cell SLC MLC-2 MLC Data Bytes per Operation (Page Size * # of Planes) Sequential Programming Throughput (MB/s) August

7 Larger Block Sizes Can Impact Random Write Performance Block Copy Time (ms) Controllers translate host logical block addresses (LBAs) to NAND Flash s physical address space Systems that use large DRAM buffers, like SSDs, are able to do this efficiently Systems that use smaller SRAM buffers, like emmc and SD cards, are not as efficient For systems with a small logical-to-physical (L2P) translation buffer, as the NAND block size increases, random write performance decreases 1. Number of pages per block (most significant factor) 2. Increase of tprog 3. Increase in I/O transfer time due to larger pages (effect not shown below) In order to reuse a block, it must be erased; all valid data must be copied out of it first Some card interfaces have write timeout specs at 250ms To improve random performance, block management algorithms manage pages or partial 1000 blocks / / 250 SLC MLC-2 MLC-3 64 / / / / / / 900 Pages per Block / tprog (typ) Block Copy Time (ms) 256 / / / August / 2000+

8 Read Latency (µs) Slowing Array Operations Increase Random Read Latencies Most applications favor read operations over write operations Most read operations are 4KB data sectors As monolithic NAND density increases, less NAND die are being used for a fixed system density As tprog increases, the latency of random 4KB sector reads becomes more variable in mixed-operation environments as the probability of needing to read from a die that is busy increases 1,800 1,600 1,400 1,200 1, Random 4KB Read Latency 25 / / / / / 1, / 1,500 Min Latency tr / tprog (µs) Max Latency USA August

9 MT/s Single Channel Package 1,600 1,400 1,200 1, NV-SDR Faster Interface Speeds Reduce Latencies and Increase Read Throughput NV-DDR Dual Channel Package ONFI 1.0 ONFI 2.x ONFI 3.0 ONFI 4.0 NV-DDR2 NV-DDR3 Read operations are still interface limited when two or more NAND die share the same I/O bus Almost all SSDs today use NAND interface speeds of 200MT/s or faster Some systems prefer multiple channels per package 2-channel BGA 4-channel BGA ONFI 4.0 is in definition Up to 800MT/s throughput Reduces energy per bit with 1.2V interface August

10 Number of Electrons Fewer Electrons Per Cell Require More ECC to Maintain Data Retention and Endurance Process shrinks lead to less electrons per floating gate ECC improves data retention and endurance To adjust for increasing RBERs, ECC is increasing exponentially to achieve equivalent UBERs As ECC requirements increase, the spare area per NAND page continues to increase ECC algorithms are transitioning from BCH to LDPC and codeword sizes are increasing 10,000 1, MLC-2 SLC Endurance (cycles) 100,000 10,000 1,000 SLC Endurance SLC ECC MLC-2 Endurance MLC-2 ECC August ECC (bits)

11 NAND Flash Trends Can Be At Odds with SSD Requirements SSD densities aren t scaling as fast as NAND Flash The SSD interface is transitioning from SATA to PCIe providing higher interface bandwidth Market pressure to make each new generation of SSD faster than the one before Can be mitigated by using the second largest monolithic die density on a process node instead of the largest SSD by Density Shipment (Units) 100% 80% 60% 40% 20% 0% Source: isuppli 1Q13, for desktop, notebook, and ultrathin combined 1TB 512GB 256GB 128GB 64GB 32GB 16GB 8GB Node NAND Density Data size # of Die Seq Write (MB/s) Gen 1 32Gb (4GB) Gen 2 64Gb (8GB) 16, Gen 3 128Gb (16GB) 32, Gen 3 64Gb (8GB) 32, August

12 Has NAND Scaling Hit the Wall? NAND will continue to scale using 3D structures, stacked like high-rise buildings Future architecture, performance, and reliability trends are similar to those of today USA August

13 Questions? August

14 About Michael Abraham Architect in the NAND Solutions Group at Micron Covers advanced NAND Flash and emerging memories IEEE Senior Member BS degree in Computer Engineering from Brigham Young University Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. Information, products and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. August