HD Video/Audio System-on-Chip (SoC) Basic Functional Analysis

Transcription

1 HD Video/Audio System-on-Chip (SoC) Basic Functional Analysis Sample Report For any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Table of Contents Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Device Summary 1.5 Observed Critical Dimensions 2 Device Identification 2.1 Package 2.2 Die 3 Process 3.1 Overview 4 Statement of Measurement Uncertainty and Scope Variation About Chipworks

3 Overview Overview 1.1 List of Figures 2 Device Identification Digital Media Player Top Digital Media Player Bottom Digital Media Player Front View Digital Media Player Back View Digital Media Player Main Circuit Board Chip on Main PCB Package Top Package Bottom Package X-Ray Die Photograph Die Markings A Die Markings B Die Corner Minimum Pitch Bond Pads 3 Process General Device Structure Minimum Pitch Metal Minimum Gate Length Transistor Minimum Contacted Gate 1.2 List of Tables 1 Overview Device Identification Device Summary Observed Critical Dimensions

4 Overview Introduction This report is a functional analysis (FAR) of the XXXX high definition (HD) video/ audio system-on-chip (SoC) solution for satellite, IP, and cable DVR set-top boxes, with watch and record DVR devices. According to XXXX, the XXXX provides a complete SoC solution for advanced multiformat decoders supporting HD/standard definition (SD) audio and video processing, combined with fast data transfer. The device features high-speed 1100-DMIPS MIPS32/MIPS16e TM graphics processors, advanced dual-stream multiformat (MPEG-4, -2, VC-1 and AVS-compliant) video decoders, a 2D graphics engine, flash memory support, dual fast Ethernet DDR2 interface ports including a high-speed 400 Mhz DDR2 memory controller, along with HD and SD audio and video outputs. The XXXX was manufactured using an eight metal (seven copper, one aluminum), 65 nm CMOS process. The device features 70 nm minimum gate length MOS transistors. This report contains the following detailed information: Package photographs, package X-ray, die markings, die photograph, and die photographs with annotated functional blocks and memories Measurements of vertical and horizontal dimensions of major microstructural features Scanning electron microscopy (SEM) cross-sectional micrographs of dielectric materials, major features, transistors, and plan-view micrographs of the part delayered to metal 1 level All of the analysis for this report was performed on two parts, with the following markings: Table Device Identification Device Package markings Die markings Date code Device Identification XXXX XXXX XXXX XXXX Table Device Identification

5 Overview Device Summary Table Device Summary Manufacturer Foundry Part number Type Date code Package markings Package type Package dimensions Die markings Device Summary XXXX XXXX XXXX ASIC CN0843 XXXX 976-pin µbga 35 mm x 35 mm x 2.7 mm XXXX Die size (die edge seal) 9.07 mm (l) x 7.89 mm (w) x 0.78 mm (t) Process type CMOS Number of metal layers 8 (7 damascene Cu and Al bond pad) Number of poly layers 1 Minimum transistor gate 0.07 µm Process generation 65 nm Feature measured to determine process generation Transistor gate length and minimum contacted gate pitch Table Device Summary

6 Overview Observed Critical Dimensions Table Layers Observed Critical Dimensions Minimum Width (µm) Observed Critical Dimensions Minimum Space (µm) Minimum Pitch (µm) Thickness (µm) Metal Metal Metal Metal Metal Metal Metal Metal Contacts Contacted 0.24 gate pitch Polysilicon Isolation (STI) Table Observed Critical Dimensions

7 Device Identification Device Identification 2.1 Package Figure through Figure show photographs of the top, bottom, and the two side views of the XXXX digital media player, from which the XXXX device was taken. The XXXX digital media player has two slots on its front side, one for a USB connection and the other is a smart card reader. There is a slot for a second USB connection and multi format video and audio outputs, including HDMI output, an audio input, and a slot for ethernet connection on the backside of the XXXX. Figure 2.1.1Digital Media Player Top Figure Digital Media Player Top Figure Digital Media Player Top

8 Device Identification 2-2 Figure 2.1.2Digital Media Player Bottom Figure Digital Media Player Bottom Figure Digital Media Player Bottom

9 Device Identification 2-3 Figure 2.1.3Digital Media Player Front View Figure Digital Media Player Front View Figure Digital Media Player Front View Figure 2.1.4Digital Media Player Back View Figure Digital Media Player Back View Figure Digital Media Player Back View

10 Device Identification 2-4 The packaged XXXX was mounted on the main printed circuit board (PCB) of the XXXX, shown in Figure and. Figure 2.1.5Digital Media Player Main Circuit Board Figure Digital Media Player Main Circuit Board Figure Digital Media Player Main Circuit Board

11 Device Identification 2-5 Figure 2.1.6Chip on Main PCB Figure Chip on Main PCB Figure Chip on Main PCB

12 Device Identification 2-6 Top and Bottom photographs of the XXXX package are shown in Figure and Figure The 976 pin micro ball grid array (BGA) package is 35 mm x 35 mm. The package markings include: XXXX Figure 2.1.7Package Top Figure Package Top 3.5 cm 3.5 cm Figure Package Top

13 Device Identification 2-7 Figure 2.1.8Package Bottom Figure Package Bottom Figure Package Bottom

14 Device Identification 2-8 A plan-view X-ray photograph is shown in Figure The XXXX die was flipchip mounted on the PCB of the XXXX package. Figure 2.1.9Package X-Ray Figure Package X-Ray Figure Package X-Ray

15 Device Identification Die Figure shows a photograph of the XXXX die. The die is 9.02 mm x 7.84 mm as measured from the die seals, or 9.07 mm x 7.89 mm for the whole die. This yields a die area of 70.7 mm 2 within the die seals. Bond pads are arranged in a grid across the surface of the die. Figure 2.2.1Die Photograph Figure Die Photograph flip-chip bond pads Figure Die Photograph

16 Device Identification 2-10 The die markings are shown in Figure and Figure These include: XXXX Figure 2.2.2Die Markings A Figure Die Markings A Figure Die Markings A Figure 2.2.3Die Markings B Figure Die Markings B Figure Die Markings B 50 µm

17 Device Identification 2-11 Figure shows an optical image of a typical die corner. A die seal is visible inside the scribe lane around the periphery of the die. Figure 2.2.4Die Corner Figure Die Corner bond pad die seal Figure Die Corner

18 Device Identification 2-12 Figure is an optical image showing the 181 µm minimum pitch bond pads. The die utilizes bond pads that are shaped as squares and octagons. The square shaped bond pads measure 95 µm x 95 µm. The octagonal shaped bond pads, with the length of the octagon measuring 39 µm, cover an area of 7,340 µm 2. The opened window of all the bond pads is octagonal in shape, with the length of the octagon measuring 25 µm and covering an area of 3,020 µm 2. Figure 2.2.5Minimum Pitch Bond Pads Figure Minimum Pitch Bond Pads 39 µm 25 µm 95 µm 95 µm 181 µm Figure Minimum Pitch Bond Pads

19 Process Process 3.1 Overview Figure shows a cross-sectional view of the XXXX. The device is fabricated using seven levels of copper interconnect plus aluminum bond pad metal. Figure 3.1.1General Device Structure Figure General Device Structure passivation 0.90 µm M8 Al M7 Cu M6 Cu M5 Cu M4 Cu M2 Cu M3 Cu STI poly M1 Cu Figure General Device Structure

20 Process 3-2 Figure shows the 0.18 µm minimum pitch metal 1. Figure 3.1.2Minimum Pitch Metal 1 Figure Minimum Pitch Metal µm M1 Cu 0.11 µm W contact PMD 0.56 µm STI Figure Minimum Pitch Metal 1

21 Process 3-3 Figure 3.1.3Minimum Gate Length Transistor Figure Minimum Gate Length Transistor W contact CoSi2 CoSi 2 70 nm STI likely nitride liner SWS nitride Figure Minimum Gate Length Transistor

22 Process 3-4 Figure shows the 0.24 µm observed minimum contacted gate pitch and butted contacts used for this part. Figure 3.1.4Minimum Contacted Gate Figure Minimum Contacted Gate W contacts butted W contacts 0.24 µm 75 nm STI likely nitride liner Figure Minimum Contacted Gate

23 Statement of Measurement Uncertainty and Scope Variation Statement of Measurement Uncertainty and Scope Variation Statement of Measurement Uncertainty Chipworks calibrates length measurements on its scanning electron microscopes (SEM), transmission electron microscope (TEM), and optical microscopes, using measurement standards that are traceable to the International System of Units (SI). Our SEM/TEM cross-calibration standard was calibrated at the National Physical Laboratory (NPL) in the UK (Report Reference LR0304/E /SEM4/190). This standard has a 146 ± 2 nm (± 1.4%) pitch, as certified by NPL. Chipworks regularly verifies that its SEM and TEM are calibrated to within ± 2% of this standard, over the full magnification ranges used. Fluctuations in the tool performance, coupled with variability in sample preparation, and random errors introduced during analyses of the micrographs, yield an expanded uncertainty of about ± 5%. A stage micrometer, calibrated at the National Research Council of Canada (CNRC) (Report Reference LS ), is used to calibrate Chipworks optical microscopes. This standard has an expanded uncertainty of 0.3 µm for the stage micrometer s 100 µm pitch lines. Random errors, during analyses of optical micrographs, yield an expanded uncertainty of approximately ± 5% to the measurements. Statement of Scope Variation Due to the nature of reverse engineering, there is a possibility of minor content variation in Chipworks standard reports. Chipworks has a defined table of contents for each standard report type. At a minimum, the defined content will be included in the report. However, depending on the nature of the analysis, additional information may be provided in a report, as value-added material for our customers.

24 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com