Introduction to Data Converter

Transcription

1 Session-06 Introduction to Data Converter Session delivered by: Chandramohan P. 1

2 Session Topics To understanding the concepts of Introduction to ADC and DAC DAC specifications ADC specifications 2

3 Session Topics Introduction to ADC and DAC DAC specifications ADC specifications Types of ADCs and DACs Limitations of ADC and DAC in high frequency applications Trade off 3

4 Introduction to ADC and DAC (a) Analog signal is filtered by an anti-aliasing filter to remove any highfrequency components that may cause an effect known as aliasing (b) The signal is sampled and held and then converted into a digital signal (c) DAC converts the digital signal back into an analog signal (d) The output of the DAC is not as "smooth" as the original signal. A lowpass filter returns the analog signal back to its original form 4

5 Converting Analog Signal to Digital Signal (a) An analog signal representing the temperature where you live (b) A digital representation of the analog signal taking one sample per day with two quantization levels. If 0 F < T < 25 F Temperature is recorded as cold If 25 F < T < 50 F Temperature is recorded as hot Discretized version of the weather is not an accurate representation of the actual weather. 5

6 Converting Analog Signal to Digital Signal cont. (a) Two samples per day with four quantization levels (b) Nine samples per day with 25 quantization levels. Increasing both sampling time and resolution, the difference between the analog and the digital signals would become negligible 6

7 Analog-to-Digital Converter Specifications And Terminology Sampling Specs: Conversion Time, Acquisition Time, Throughput Rate, Aperture Delay, Aperture Jitter, Step Response DC Specs: Specifications derived from ADC tests using DC/low freq test signals Gain Error, Offset Error, INL, DNL AC Specs: Specifications derived from ADC tests using sine wave test signals SNR, SINAD, ENOB 7

8 Sample-Hold Operation All S/H s require 4 main components: Buffer Amp: buffers source & provides high current gain to charge the hold capacitor Hold Capacitor: Retains the sampled voltage in Hold mode Output Buffer: High impedance to keep held voltage from discharging Switch & Control: Mechanism by which the hold capacitor is switched from track to hold 8

9 Sample-Hold Specifications Errors in Sample-to- Hold Aperture Jitter Aperture Error Errors in Hold-to- Sample Acquisition time 9

10 Sample-to-Hold Transition Errors Aperture Uncertainty ( Jitter ) The RMS variation in time of the sampling instant Caused by jitter in the Sample-Hold command signal Places an upper limit on the input frequency to maintain system resolution for full scale input signals. 10

11 Aperture Jitter For +/ LSB Error 11

12 Aperture Jitter Effects Comparison of different clock sources Good clock source Not so good clock source 12

13 Hold-to-Sample Transition Errors Acquisition Time The length of time during which time the S/H must remain in the sample mode in order for the HOLD CAPACITOR to acquire a full scale step input (to some number of accuracy in LSBs) 13

14 Digital to Analog Converter An N-bit digital word is mapped into a single analog voltage. Typically, the output of the DAC is a voltage that is some fraction of a reference voltage (or current) V out = FV REF Where, V OUT is the analog voltage output VREF is the reference volt F is the fraction defined by the input word, D, that is N bits wide 14

15 Number of inputs The number of input combinations represented by the input word D is related to the number of bits in the word by Number of input combinations = 2 N Example: 4-bit DAC has a total of 2 4 or 16 total input values. A converter with 4-bit resolution must be able to map a change in the analog output, which is equal to 1 part in 16. The maximum analog output voltage for any DAC is limited by the value of V REF. If the input is an N-bit word, then the value of the fraction, F, can be determined by, F = D 2 N 15

16 Full Scale Range Example: A 3-bit DAC is being used, the input, D, is 100 = 4 10, and V REF is 5 V, then the value of F is 100 F = 2 3 = The analog voltage that appears at the output is (5) 8 = = = VOUT 2.5V The maximum analog output voltage that can be generated is known as Full-scale voltage, V FS, and can be generalized to any N-bit DAC as V FS = 2 2 N 1 N V REF 16

17 Least Significant Bit (LSB) The Least Significant Bit (LSB) refers to the rightmost bit in the digital input word. The LSB defines the smallest possible change in the analog output voltage. The LSB will always be denoted as D 0. One LSB can be defined as 1 LSB = V 2 Example: Find the resolution for a DAC if the output voltage is desired to change in 1 mv increments while using a reference voltage of 5 V. The DAC must resolve The accuracy required for 1 LSB change over a range of V REF is 1LSB V REF = REF N 1mV 5V N = =

18 Least Significant Bit (LSB) Solving N for the resolution yields 5V 1mV N = Log = bits which means that a 13-bit DAC will be needed to produce the accuracy capable of generating 1 mv changes in the output using a 5 V reference. Example: Find the number of input combinations, values for 1 LSB, the percentage accuracy, and the full-scale voltage generated for a 3-bit, 8-bit, and 16-bit DAC, assuming that V REF = 5 V 18

19 D/A Specifications Cont Ideal transfer curve for a 3-bit DAC Differential Nonlinearity for 3 Bit DAC DNLn = Actual increment height of transition n - Ideal increment height 19

20 D/A Specifications Cont DNLn = Actual increment height of transition n - Ideal increment height DNL 3 =1.5 LSB - 1 LSB = 0.5 LSB DNL 4 = 0.5 LSB - 1 LSB = LSB DNL 5 = 0.25 LSB - 1 LSB = LSB DNL 6 = 1.75 LSB - 1 LSB = 0.75 LSB DNL 1, DNL 2 and DNL 7 = 1 LSB - 1 LSB =0 DNL curve for the nonideal 3-bit DAC 20

21 D/A Specifications Cont Integral Nonlinearity INLn = Output value for input code n - Output value of the reference line at that point Measuring the INL for a DAC transfer curve Example of integral nonlinearity for a DAC 21

22 DC Specifications: Offset Error Offset Error The analog output should be 0 V for D = 0. However, an offset exists if the analog output voltage is not equal to zero 22

23 DC Specifications: Gain Errors Gain Error A gain error exists if the slope of the best-fit line through the transfer curve is different from the slope of the best-fit line for the ideal case Gain error = Ideal slope - Actual slope 23

24 Latency DC Specifications This specification defines the total time from the moment that the input digital word changes to the time the analog output value has settled to within a specified tolerance Latency should not be confused with settling time, since latency includes the delay required to map the digital word to an analog value plus the settling time. It should be noted that settling time considerations are just as important for a DAC as they are for a S/H or an operational amplifier. 24

25 D/A Specifications Dynamic Range Dynamic range is defined as the ratio of the largest output signal over the smallest output signal. For both DACs and ADCs, the dynamic range is related to the resolution of the converter. For example, an N-bit DAC can produce a maximum output of 2N 1 multiples of LSBs and a minimum value of 1 LSB. Therefore, the dynamic range in decibels is simply 2 n 1 DR 20log = = N.dB A 16-bit data converter has a dynamic range of db. 25

26 ADC Evaluation System Signal Source ADC Analysis Engine The most common method for quantifying these dynamic errors is by applying a pure sine-wave signal to the ADC and performing an FFT on the output data. These tests yield spectral outputs from which we can calculate the S/N ratio, harmonic distortion and SINAD. Evaluation Results 26 14

27 D/A Specifications Cont Signal-to-Noise Ratio (SNR) Signal-to-noise (SNR) is defined as the ratio of the signal power to the noise at the analog output Signal-to-noise (SNR) ratios of ADCs represent the value of the largest RMS input signal into the converter over the RMS value of the noise. SNR = 6.02N db For 16-bit data conversion, one must design a circuit that will have an SNR of (6.02)(16) = db Effective number of bits given a system with a known SNR or SNDR, For 16-bit ADC yielded an SNDR of 88 db, then the effective resolution of the converter would be N = ( )/6.02 = bits 27

28 AC Specs: Signal to Non-Harmonic Noise Ratio (SNR, or SNHR) M 2 Fundamental RMS noise = Σ Non Harmonic Bins 2nd Harm. 3rd Harm. 4th Harm. 5th Harm. khz SNR (db) = 20 LOG ( Fund. rms / rms noise) i.e. no Harmonics Included Indication of Converter Noise Floor NO Indication of Dynamic Range

29 AC Specs: Total Harmonic Distortion (THD) M 2 Fundamental Distortion rms =Σ Harmonic Bins 2 to 10 2nd Harm. 3rd Harm. 4th Harm. 5th Harm. khz THD (%) = (Harmonic RMS Noise / Fundamental RMS) x 100 i.e. - Contains only Harmonic Components THD is an indication of the ADC non-linearities

30 AC Specs: Signal to Noise + Distortion (SINAD) M 2 Fundamental Noise + D = Σ of all bins except fundamental 2nd Harm. 3rd Harm. 4th Harm. 5th Harm. khz SNR+D (db) = 20 LOG ( Fundamental rms / (rms noise + harmonics)) i.e. - includes all error components Indication of Converter useful Dynamic Range

31 AC Specs: Spurious Free Dynamic Range (SFDR) SFDR = Spurious Free Dynamic Range Magnitude of the largest harmonic relative to the fundamental In this case, about 50dB = 0.32% 31

32 Frequency Dependent Errors ADS8344 (16-bit, 100kSPs) ADS8344 A/D Converter Ideal 16-bit resolution= 98 db SNR 32

33 Effort Required to Achieve a Certain ENOB 33

34 ADC specifications Block diagram of the analog-to-digital converter Number of quantization levels = 2 N 34

35 ADC specifications Transfer Curve for an ideal ADC and its corresponding quantization error 1 LSB = V 2 REF N 35

36 ADC specifications Cont Quantization Error The analog input is an infinite valued quantity and the output is a discrete value, an error will be produced as a result of the quantization. This error, known as quantization error, Q e, is defined as the difference between the actual analog input and the value of the output (staircase) given in voltage. It is calculated as Q e = V in -V staircase where the value of the staircase output, Vstaircase, can be calculated V V 2 REF = D. = D. staircase N V LSB 36

37 ADC specifications Cont Differential Nonlinearity Differential nonlinearity for an ADC is similar to that defined for a DAC. However, for the ADC, DNL is the difference between the actual code width of a nonideal converter and the ideal case DNL = Actual step width - Ideal step width Since the step widths can be converted to either volts for LSBs, DNL can be defined using either units. The value of the ideal step is 1/8. Converting to volts, this becomes V idealstepwidth = 1/8 * V REF = V= 1 LSB 37

38 ADC specifications Cont DNL Example: Calculate the differential nonlinearity of the 3-bit ADC. Assume that V REF = 5V. DNL 2 = 1.5 LSB - 1 LSB = 0.5 LSB DNL 3 = 0.5 LSB - 1 LSB = LSB DNL 5 = -0.5 LSB DNL 6 = 0.5 LSB 38

39 ADC specifications Cont Missing Codes It is of interest to note the consequences of having a DNL that is equal to -1 LSB The total width of the step corresponding to 101 is completely missing; thus, the value of DNL5 is -1 LSB 39

40 ADC specifications Cont Integral Nonlinearity Integral nonlinearity (INL) is defined similarly to that for a DAC. Again, a "best-fit straight line is drawn through the end points of the first and last code transition, with INL being defined as the difference between the data converter code transition points and the straight line with all other errors set to zero. INL0 = 0 INL1 = 0 INL2 = 0 INL4 = 0 INL5 = 0 INL7 =0 INL3= 3/8-5/16 = 1/16 or 0.5 LSB INL6= - 0.5LSB 40

41 ADC specifications Cont Offset and Gain Error Offset error occurs when there is a difference between the value of the first code transition and the ideal value of 1/2 LSBs Offset error is a constant value. the quantization error becomes ideal after the initial offset voltage is overcome Gain error or scale factor error, is the difference in the slope of a straight line drawn through the transfer characteristic and the slope of 1 of an ideal ADC. 41

42 Distortion and Linearity x( t) = Asin( ωt) Imperfect (non-linear) system 2 3 y ( t) = a1x( t) + a2 x ( t) + a3x ( t) A Linear System: Sine wave in = Sine wave out Amplitude may be reduced Phase shifted A non-linear system will distort a signal Sine wave in = Sine wave out+harmonics at integer multiples of the fundamental frequency This THD (Total Harmonic Distortion) of the signal is a measure of the linearity of the system 42

43 Metrics for Distortion THD = Total Harmonic Distortion Measure of the power of all harmonics relative to the fundamental (usually a full scale input signal) THD = P Harmonics _ Total P Fundamental THD db Vh2 + Vh3 + Vh log V f = 2 SFDR = Spurious Dynamic Range Magnitude of the largest harmonic relative to the fundamental In this case, about 50dB = 0.32% THD Vh2 + Vh3 + Vh % = THD Spec: compute for first 9 harmonics (h2 through h10) V f 43

44 Noise Sources Interference noise External sources, not easily controlled Inherent noise Many sources (1/f, Thermal Noise, Op- Amp Noise, Quantization Noise, Aperture Noise ) Noise depends on the bandwidth you re working with. Resistance noise E rms = 0.13 [R(f 2 -f 1 )] µv R in MΩ (f 2 -f 1 ) in room temp To illustrate this over a 50-kHz range, the noise generated by a 10- kω resistor is around 2.9 µv. Reference voltage 2.7v 3.6v 5v 1LSB 41.2 µv 54.9 µv 76.3 µv 16- bit LSB resolution 44

45 Total Noise The combined effect of several random noise sources is found by root sum of the squares addition of the rms values of the separate noise sources. E = ( E E 22 + E ) total The largest noise sources are dominant

46 System Purity Summary Linearity (THD or SFDR) Is a measure of how much a system distorts a signal. Dynamic Range or Resolution is a measure of the largest signal a system can handle, to the smallest that can be discerned from noise, THD etc. Both can be expressed in bits (i.e. how accurate would an A/D converter need to be to achieve the same linearity or resolution?) 8 bit accuracy = 1 in 2 8 = 0.39% = -48dB 12 bit accuracy = 1 in 2 12 = 0.024% = -72dB 16 bit accuracy = 1 in 2 16 = % = -96dB 46

47 Analog/Digital Conversion Interface In order to process an analog signal in the digital domain, we need to convert an analog signal to a digital signal via a process called analog-to-digital conversion, where sampling & quantization are the fundamental processes In order to reproduce an analog signal after processing, we use the reverse process of digital-to-analog conversion, where interpolation is the fundamental process 47

48 Basic Analog-to-digital Conversion Blocks Sampler Samples the signal at discrete time intervals Quantizer Approximates the sampled voltage with a level from a fixed set of 2 n possible voltage levels via ROUNDING or TRUNCATION Encoder Encodes the measurement in a convenient format for communication or processing 48

49 Sampling Schemes Impulse Sampling (Theoretical not implemented in practice) Natural Sampling (Theoretical - multiplier is a switch) Zero-order hold Sampling (Ideal Sample/Hold - instantaneous acquisition time is impractical) Track/Hold (Real Sample/Hold Result is sampled and stored in a memory element) 49

50 So..What Frequency Do I Sample At? Generally, faster is better, but... Limited by physical constraints Switch resistance Amplifier settling time Required component values Rule of thumb: sample at greater than 10X signal BW minimises sampling effects (amplitude distortion) eases the anti-aliasing filter requirements (reduced filter order) 50

51 Common Sampling Rates Which rates can represent the range of frequencies audible by (fresh) ears? Sampling Rate Uses 44.1 khz (44100) CD, DAT 48 khz (48000) DAT, DV, DVD-Video 96 khz (96000) DVD-Audio khz (22050) Old samplers Most software can handle all these rates. 51

52 3-bit Quantization A 3-bit binary (base 2) number has 2 3 = 8 values. 7 6 Amplitu ude Time measure amp. at each tick of sample clock A rough approximation 52

53 4-bit Quantization A 4-bit binary number has 2 4 = 16 values Amplitu ude Time measure amp. at each tick of sample clock A better approximation 53

54 Quantization Noise Round-off error: difference between actual signal and quantization to integer values Random errors: sounds like low-amplitude noise 54

55 Common Sampling Resolutions Word length 8-bit integer 16-bit integer 24-bit integer 32-bit floating point Uses Low-res web audio CD, DAT, DV, sound files DVD-Video, DVD-Audio Software (usually only for internal representation) 55

56 16-bit Sample Word Length A 16-bit integer can represent 2 16, or 65,536, values (amplitude points). Typically use signed 16-bit integers, and center the 65,536 values around 0. 32, ,768 56

57 CD characteristics Audio File Size - Sampling rate: 44,100 samples per second (44.1 khz) - Sample word length: 16 bits (i.e., 2 bytes) per sample - Number of channels: 2 (stereo) How big is a 5-minute CD-quality sound file? 57

58 Audio File Size How big is a 5-minute CD-quality sound file? 44,100 samples * 2 bytes per sample * 2 channels = 176,400 bytes per second 5 minutes * 60 seconds per minute = 300 seconds 300 seconds * 176,400 bytes per second = 52,920,000 bytes = c megabytes (MB) 58

59 Quantization of Continuous Amplitude Signals A digital signal is a sequence of numbers (samples) in which each number is represented by a finite number of digits (finite resolution) The process of converting a discrete-time continuousamplitude signal into a digital signal is called quantization The error introduced in representing the continuousvalued signal by a finite set of discrete values is called quantization error, or quantization noise 59

60 Unipolar, Linear, Uniform Quantizer (& Binary Coder) Linear progression of quantization steps of Uniform width Max. input voltage = V ref Quantizer step width,, refers to the minimum change in input to change output code by 1, given by = V ref 2 m ADC DC specs derived from non-ideal transfer function 60

61 Effect of Amplitude Quantization Quantizer error signal depends on the input signal dynamic range and #quantization levels With high #levels, the error signal is modeled as an additive noise signal with a uniform probability distribution Quantization error signal power is given by it s variance 2 σ e = / 2 2 e / 2 / p( e) de = e de / 2 =

62 SNR q : Quantizer Output Signal-to-Noise Ratio (Full Scale Sinusoidal Input) Input Signal: Full Scale Sinusoid Peak ampl=v ref/2 Input signal power: Derivation of SNR SNR q P = σ 3 av 2m = e P AV = ( V 2 ) ref Quantization noise power: Derivation of SNR in decibels 3 2m SNR q ( db) = 10log m / σ e = 12 = 2 8 = ( 10log log10 2) + 20mlog10 = m Real SNR affected by actual quantization noise PDF, as well as harmonics and aperture jitter 2 62

63 Real ADC Errors Real ADCs have other errors in addition to the nominal quantization error discussed Divided into the categories of STATIC & DYNAMIC, depending on the rate of change of the input signal at time of digitization STATIC errors usually result from non-ideal spacing of code transition levels DYNAMIC errors occur because of the additional sources of error induced by the time variation of the analog signal being sampled Harmonic distortion from the S/H stage Signal-dependent variations in the sample instant Frequency-dependent variation in the spacing of the quantization levels 63

64 64

65 Nyquist Rate Converters Converters that generate a series of output values in which each value has a one-to-one correspondence with an input value Note: These converters are seldom run at the Nyquist rate due to the difficulty in realizing practical anti-aliasing & reconstruction filters In most cases, Nyquist rate converters operate at 1.5 to 10 times the Nyquist rate (i.e. 3 to 20 times the input signal s bandwidth) Examples: Flash Pipelined Successive Approximation (SAR) 65

66 Oversampling Converters Converters that operate much faster than the input signal s Nyquist rate (typically 20 to 512 times faster) Increase the output SNR by digitally filtering out quantization noise that s not in the signal s bandwidth Use noise shaping to place much of the quantization noise outside the input signal s bandwidth Example Sigma-delta 66

67 Nyquist vs. Oversampling Major advantage of oversampling ADCs is that they allow the specifications of the input anti-aliasing filter to be relaxed Lowers the implementation cost 67

68 68

69 Which ADC Architecture to Use?? Summary & Approximate Ranking: Characteristic Flash Pipeline d SAR Sigma Delta Throughput (samples/sec) Resolution (ENOB) Latency (Sample-to-Output) Suitability for converting Multiple Signals per ADC Capability to convert nonperiodic multiplexed signals Simplified anti-aliasing filter requirements ** Power Consumption Constant Constant Scales with Sample Rate Constant 69

70 Summary Increasing both sampling time and resolution, the difference between the analog and the digital signals would become negligible DC Specifications: Specifications derived from ADC tests using DC/low freq test signals Gain Error, Offset Error, INL, DNL AC Specifications: Specifications derived from ADC tests using sine wave test signals SNR, SINAD, ENOB In order to process an analog signal in the digital domain, we need to convert an analog signal to a digital signal via a process called analog-to-digital conversion, where sampling & quantization are the fundamental processes 70

71 Summary Cont In order to reproduce an analog signal after processing, we use the reverse process of digital-to-analog conversion, where interpolation is the fundamental process Sampler Samples the signal at discrete time intervals Quantizer Approximates the sampled voltage with a level from a fixed set of 2 n possible voltage levels via ROUNDING or TRUNCATION Encoder Encodes the measurement in a convenient format for communication or processing 71