Low Power Design. in CMOS. Digital Integrated Circuits Low Power Design

Transcription

1 Low Power Design in CMOS

2 Why worry about power? -- Heat Dissipation source : arpa-esto microprocessor power dissipation DEC 21164

3 Evolution in Power Dissipation

4 Why worry about power Portability BATTERY (40+ lbs) Multimedia Terminals Laptop Computers Digital Cellular Telephony Nominal Capacity (Watt-hours / lb) Rechargable Lithium Nickel-Cadium Ni-Metal Hydride Year Expected Battery Lifetime increase over next 5 years: 30-40%

5 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors

6 Dynamic Power Consumption Vdd Vin Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power.

7 Dynamic Power Consumption - Revisited Power = Energy/transition * transition rate = C L * V 2 dd * f 0 1 = C L * V 2 dd * P 0 1 * f = C EFF * V 2 dd * f Power Dissipation is Data Dependent Function of Switching Activity C EFF = Effective Capacitance = C L * P 0 1

8 Power Consumption is Data Dependent Example: Static 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: C EFF = 3/16 * C L P(Out=1) = 1/4 P(0 1) = P(Out=0).P(Out=1) = 3/4 1/4 = 3/16

9 Transition Probabilities for Basic Gates

10 Transition Probability of 2-input NOR Gate

11 Problem: Reconvergent Fanout A X B Z Reconvergence P(Z=1) = P(B=1). P(X=1 B=1) Becomes complex and intractable real fast

12 How about Dynamic Circuits? V DD φ M p Out In 1 In 2 In 3 PDN φ M e Power is Only Dissipated when Out=0! C EFF = P(Out=0).C L

13 4-input NAND Gate Example: Dynamic 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=0) = 3/4 C EFF = 3/4 * C L Switching Activity Is Always Higher in Dynamic Circuits

14 Transition Probabilities for Dynamic Gates Switching Activity for Precharged Dynamic Gates P 0 1 = P 0

15 Glitching in Static CMOS also called: dynamic hazards A X B C Z ABC X Z Unit Delay Observe: No glitching in dynamic circuits

16 Example 1: Chain of NOR Gates 1 out1 out2 out3 out4 out V (Volt) out2 out8 out6 out4 out1 out3 out t (nsec) out7

17 Example 2: Adder Circuit C in Add0 Add1 Add2 Add14 Add15 S0 S1 S2 S14 S15 Sum Output Voltage, Volts Cin S Time, ns 6 5 S10 S15

18 How to Cope with Glitching? 0 0 F 1 1 F F F 1 F F 3 Equalize Lengths of Timing Paths Through Design

19 Short Circuit Currents Vdd Vin Vout C L 0.15 I VDD (ma) V in (V)

20 Impact of rise/fall times on short-circuit currents V DD V DD I SC 0 I SC I MAX V in V out V in V out C L C L Large capacitive load Small capacitive load

21 Short-circuit energy as a function of slope ratio E / E V DD = 5 V V DD = 3.3 V r W/L P = 7.2µm/1.2µm W/L N = 2.4µm/1.2µm The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals.

22 Static Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=1).V dd. I stat Dominates over dynamic consumption Not a function of switching frequency

23 Leakage Vdd Vout Drain Junction Leakage Sub-Threshold Current Sub-Threshold Current Dominant Factor

24 Sub-Threshold in MOS ID V T =0.2 V T =0.6 V GS Lower Bound on Threshold to Prevent Leakage

25 Power Analysis in SPICE i DD + - V DD Circuit Under Test k i DD C R P av Equivalent Circuit for Measuring Power in SPICE

26 Design for Worst Case V DD V DD A B 2 A B F C L A D B 2 C D 2 A 1 B C 2 F Here it is assumed that R p = R n

27 Reducing V dd NORMALIZED POWER-DELAY PRODUCT quadratic dependence 51 stage ring oscillator 8-bit adder Vdd (volts) P x t d = E t = C L * V dd 2 E(Vdd=2) E (Vdd=5) (C L ) * (2) 2 = (CL) * (5) 2 E(Vdd=2) 0.16 E(Vdd =5) Strong function of voltage (V 2 dependence). Relatively independent of logic function and style. Power Delay Product Improves with lowering V DD.

28 Lower V dd Increases Delay multiplier clock generator 2.0µm technology T d = C L * V dd I NORMALIZED DELAY adder ring oscillator adder (SPICE) microcoded DSP chip T d(vdd=2) = (2) * (5-0.7) 2 T d(vdd=5) I ~ (V dd - V t ) 2 4 (5) * (2-0.7) V dd (volts) Relatively independent of logic function and style.

29 Lowering the Threshold Delay I D 2V t V dd V t = 0 V t = 0.2 V GS Reduces the Speed Loss, But Increases Leakage Interesting Design Approach: DESIGN FOR P Leakage == P Dynamic

30 Transistor Sizing for Power Minimization Lower Capacitance Small W/L s Higher Voltage Higher Capacitance Large W/L s Lower Voltage Larger sized devices are useful only when interconnect dominated. Minimum sized devices are usually optimal for low-power.

31 Transistor Sizing for Fixed Throughput I W/L C MIN C g = W/L C MIN C P = C wiring + C DF C MIN = Minimum sized gate (W/L=1) W /L after sizing α = C P / (K C MIN ) HIGH PERFORMANCE W/L >> C P / (K C MIN ) LOW POWER W/L = 2 C P / (K C MIN ) (if C P K C MIN ) NORMALIZED ENERGY ELSE W/L = α = W/L adder α = 0 α = 0.5 α = 1 α = 1.5

32 Reducing Effective Capacitance Global bus architecture Local bus architecture Shared Resources incur Switching Overhead

33 Summary Power Dissipation is becoming Prime Design Constraint Low Power Design requires Optimization at all Levels Sources of Power Dissipation are well characterized Low Power Design requires operation at lowest possible voltage and clock speed