BR88 SRD AUDIO RX MHz

Transcription

1 , Via Maniago 0 Milan Italy Tel.: +.0. / / 8 Fax: BR88 SRD AUDIO RX MHz MHz AUDIO PLL RECEIVER MODULE WITH PILOT TONE DECODER (RDS) BR88V Vcc audio Rx module ( V logic interface ) BR88V Vcc audio Rx module ( V logic interface ) Frequency MHz () Sensitivity. -00 dbm (0 db SINAD) ( khz dev. 0 khz) Selectivity. ± 0 khz Modulation. FM (dev. ± 0 khz max.) Audio output level.. 0 mvrms (00 mvpp - 00kΩ load) Audio response Hz RDS data output.. 00 Baud max. Note () : 8-8 MHz audio wireless band CEPT ERC REC 0-0 annex J J 8,,,8 0,, Fig. Phisical dimensions

2 , Via Maniago 0 Milan Italy Tel.: +.0. / / 8 Fax: ANT. input (0 ohm) J TP Q Q VCO Q- MIXER - IF IC RV ICA CV DISCR. DEENF. ICB 0.uF PILOT TONE DETECTOR +Vcc 0K J Vdc ma BR88v Vdc ma BR88v AUDIO OUTPUT (00mVpp on 00Kohm LOAD) PILOT TONE DET. OUTPUT (high with pilot tone) RSSI OUTPUT (0. -. Vdc) LOCK DET. CV X.8MHz PLL IC 8 LATCH ENABLE DATA 0 CLOCK PLL CONTROL FREQ.ADJ. Fig. Functional block diagram BR IN REG. TDA0AT MUTE VOL. CONTR. OUT+ OUT- +Vdc TONE RSSI LOCK DET. LATCH EN. DATA CLOCK uc Fig. BR88 receiver electrical connections T CL (CLOCK) T INVALID DATA MSB LSB DA (SERIAL DATA) BIT BIT8 BIT T T CONTROL BIT (CNT) LE (LATCH ENABLE) T T T > 00 ns T > 00 ns T > 00 ns T > 00 ns T > 00 ns T > 00 ns "H" LEVEL >, V (BR88v) <,8 V (BR88v) "L" LEVEL < 0,8 V (BR88v) > V (BR88v)

3 Fig. - Serial interface timing diagram. STE sas ELETTRONICA TELECOMUNICAZIONI, Via Maniago 0 Milan Italy Tel.: +.0. / / 8 Fax: FREQUENCY PROGRAMMING ) The PLL frequency synthesizer Receiver local oscillator frequency is generated by a low phase-noise VCO (Voltage Controlled Oscillator) locked by a PLL circuit ( Fujitsu MBE0SL) to the reference.800 MHz Xtal (X in fig.). ) Serial control interface description A wires serial control interface (clock, data and latch enable) is used to program the PLL IC (fig.). Data are written into the -bit shift register (see fig.) at the rising edge of the CL (clock) signal (MSB first). Data are then transferred into the appropriate 8-bit latch at the rising edge of the LE (latch enable) pulse depending on the CNT (control bit) value. R latch is loaded if CNT bit is set to, N latch is loaded with CNT = 0. To program a frequency two -bit long words must be written into the shift register : the R word and the N word. "R" LATCH (8 BITS) MSB CS LDS FC SW REFERENCE COUNTER ( BITS) - BIT SHIFT REGISTER CNT "R" LATCH CONTROL BIT CNT= DATA LSB CLOCK DA CL N-PROGRAMMABLE COUNTER (8 BITS) "N" LATCH (8 BITS) "N" LATCH CONTROL BIT CNT= 0 LATCH EN. LE Fig. - PLL internal register and latches.

4 , Via Maniago 0 Milan Italy Tel.: +.0. / / 8 Fax: ) PLL frequency synthesizer parameters PLL IC Reference frequency Programming frequency step : Fujitsu MBE0SL :.800 MHz : 0 khz SW bit (bit of R word) = : prescaler divide ratio = / FC bit (bit of R word) = : phase comparator positive output LDS bit (bit 8 of R word) = 0 : lock-detect signal available CS bit (bit of R word) = : charge pump current = ma Note : Although these are the reccomended parameters, different PLL programming modes can be implemented, if necessary. Refer to MBE0SL data sheet at for further informations. ) R - word Bit (CNT) must be set to. Bits from to are the R number Bits from to are the SW, FC, LDS and CS bits. R is the value that is preset into the PLL reference divider and is calculated dividing the reference frequency (800 khz) by the required minimum programming frequency step. For a 0 khz frequency step : R = 800 / 0 = (0H) R word - example Frequency step = 0 khz ( R = 0H ) CS = ( PLL charge pump current = ma) R word MSB SHIFT LSB CS LDS FC SW R CNT

5 , Via Maniago 0 Milan Italy Tel.: +.0. / / 8 Fax: ) N-word Bit (CNT) must be 0. Bits from to are the N number. N value is calculated dividing the receive required frequency minus 000 khz (the IF frequency) by the frequency step. NOTE: Due to the internal architecture of the PLL IC, when SW bit of R-WORD (bit n. ) is (prescaler divide ratio = /), bit n. 8 of N-word must not be used. It must be fixed to 0 and ignored. N word - example Receiver frequency = 8.0 MHz N = / 0 = 0 (BH) N word MSB SHIFT ( ) LSB N CNT Note ( ) : Bit n.8 is fixed to 0 and ignored.

6 , Via Maniago 0 Milan Italy Tel.: +.0. / / 8 Fax: Lock detect output ( LD J pin n. ) During normal operation, the PLL is locked to the correct programmed frequency and the LD output is high ( + V ). +V J J 0K LD V - LOCK 0V - UNLOCK MCU BC88 0V - LOCK V - UNLOCK MCU Fig. Lock detect output interface to MCU. During normal operation, it is not usually necessary to control the UNLOCK situation. An UNLOCK situation is possible during a long period of continuos reception : in this case the MCU detects the UNLOCK state and provides to resend the appropriate programming words. Note : Avoid to sample the LD status immediately after the programming sequence. A time of 00 ms or more, also between subsequent LD controls, is recommended. DISCR.ADJ. FREQ. ADJ, BR88 OUTPUT LEVEL Vcc AUDIO OUTPUT (00 mvpp) RDS OUTPUT RSSI 8 0 CL MICROPIC MODULE DA 0 LE LD 8 RXE

7 , Via Maniago 0 Milan Italy Tel.: +.0. / / 8 Fax: Fig. - BR88 receiver test setup with frequency programming from micropic module.