OmniVision OV8830 (OV2B8BQ Die Markings) 8 Mp, 1.4 µm Pixel Pitch OMNIBSI-2TM Back Illuminated (BSI) CMOS Image Sensor

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1 OmniVision OV8830 (OV2B8BQ Die Markings) 8 Mp, 1.4 µm Pixel Pitch OMNIBSI-2TM Back Illuminated (BSI) CMOS Image Sensor Imager Process Review 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

2 Imager Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR JMRK Revision 1.0 Published: March 16, 2012

3 Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 OmniVision BSI Comparison 1.6 Device Summary 1.7 Process Summary 2 Device Overview 2.1 Downstream Product, Camera Module, Package, and Die Overview 2.2 Back Die Photograph and Die Features 2.3 Die Utilization Analysis 3 Process Analysis 3.1 Overview 3.2 General Device Structure 3.3 Image Sensor Substrate and Wells 3.4 Image Sensor Substrate Isolation 3.5 Peripheral Transistors and Poly 3.6 Front Dielectrics 3.7 Front Metallization 3.8 Vias and Contacts 3.9 Wafer Bonding and Carrier Wafer 3.10 Back of Die Processing (Dielectrics and Metals) 3.11 Bond Pads 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan-View Analysis 4.3 Pixel Cross-Sectional Analysis Parallel to Transfer Lines 4.4 Pixel Cross-Sectional Analysis Parallel to Column Out Line 5 Memory Cell Analysis 5.1 Memory Cell Overview 5.2 6T SRAM Plan-View Analysis

4 Imager Process Review 6 Critical Dimensions 6.1 Image Sensor Substrate and Wells 6.2 Image Sensor Substrate Isolation 6.3 Peripheral Transistors and Poly 6.4 Front Dielectrics 6.5 Front Metallization 6.6 Vias and Contacts 6.7 Back of Die Processing (Dielectrics and Metals) 6.8 Pixel Horizontal and Vertical Directions 7 References 8 Statement of Measurement Uncertainty and Scope Variation

5 Overview Overview 1.1 List of Figures 2 Device Overview Asus Eee Pad Transformer Prime Packaging Box Front Asus Eee Pad Transformer Prime Front Asus Eee Pad Transformer Prime Back Asus Eee Pad Transformer Prime Back (Tilt View) Inside of Asus Eee Pad Transformer Prime Tablet Asus Eee Pad Transformer Prime Tablet Display Front Asus Eee Pad Transformer Prime Tablet Back Panel Asus Eee Pad Transformer Prime Tablet Main PWB Mp Camera Module Front Mp Camera Module Covered Back Mp Camera Module Exposed Back Mp Camera Module Side Mp Camera Module Planar Package X-Ray Mp Camera Module Side X-Ray Mp Camera Module with Lens Barrel Removed Plan View Mp Camera Module with Lens Barrel Removed Side View Mp Camera Module Glass Window Removed TF98 A ASIC Die Photograph TF98 A ASIC Die Markings No TF98 A ASIC Die Markings No M24128A-A 128 Kb EEPROM Die Photograph M24128A-A 128 Kb EEPROM Die Markings Back Die Photograph Color Filters and Lenses Intact Back Die Photograph Color Filters and Lenses Removed Die Markings Annotated Back Side Poly Die Photograph Analysis Sites Top Left Die Corner Overview Bottom Right Die Corner Overview Die Corner A Detail Die Corner B Detail Die Corner C Detail Die Corner D Detail Die Corner SEM Tilt View Active Pixel Array Corner Top Left Active Pixel Array Corner Bottom Right Active Pixel Array Corner Overview Plan View Active Pixel Array Corner Overview Tilt View Active Pixel Array Corner Detail Tilt View Microlenses Plan View Microlenses Tilt View

6 Overview Bayer Color Filter Array Pixel Pitch Minimum Pitch Bond Pads Bond Pad Die Bond Pad with Au Ball Bond Attached Tilt View Annotated Poly Die Photograph Overview of Standard Logic Details of a Standard Logic Cell 3 Process Analysis Die Thickness Die Edge Outer Die Seal Inner Die Seal General Structure Periphery General Structure Pixel Array SCM of Peripheral Logic N-well SCM of Peripheral Logic P-well SCM of Periphery/Pixel Array Transition Pixel Array Silicon Etch Pixel Array Silicon Etch Overview SCM of Pixel Array SIMS Analysis Sites SIMS of Periphery SIMS of Pixel Array Minimum Width STI Periphery TEM of Poly Over STI Pixel Array TEM of STI Pixel Array Logic MOS Transistor Overview Glass Etch NMOS Logic Transistors PMOS Logic Transistors TEM of Logic Transistor TEM of Sidewall Spacer (SWS) TEM of Logic Gate Oxide PMD Periphery Nitride CESL TEM of PMD Pixel Array TEM of Lower PMDs Pixel Array SEM of ILD TEM of ILD SEM of ILD 2 and ILD TEM of ILD TEM of ILD Passivation Minimum Pitch Metal TEM of Metal Minimum Pitch Metal 2

7 Overview Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Contacts TEM of Contact to Substrate from Periphery TEM of Bottom of Contact to Substrate from Periphery TEM of Bottom of Contact to Substrate from the Pixel Array TEM of Bottom of Contact to Poly Minimum Pitch Via 1s, Via 2s and Via 3s TEM of Via Carrier Wafer and Imager Die Overview Detail of Wafer Bond Interface Back Dielectrics and Metals in Periphery SEM Overview Back Dielectrics and Metals in Periphery SEM Detail AR in Pixel Array TEM BPMD-1 Over Pixel Array in Detail TEM TEM of Metal and Back Passivation TEM of Pixel AR Layer, Color Filters, and Microlenses Gold Ball Bond Overview Edge of Bond Pad Window Left Edge Edges of Bond Pad Window and Si Substrate Overview Edge of Si Substrate Detail SEM Cross Section Through Bond Pad Via Overview of the Edge of Bond Pad Via Details of the Edge of Bond Pad Via 4 Pixel Analysis Pixel Schematic Pixels at Metal Pixels at Via 3/Metal Pixels at Metal Pixels at Via 2/Metal Pixels at Metal Pixels at Via 1/Metal Pixel at Metal Pixels at Poly to Metal 1 Transition Pixels at Poly Pixel at Diffusion SCM of N-Cathode Overview SCM of N-Cathode Detail Cross Section Reference Periphery to Active Pixel Transition Overview Edge of Active Pixels Detail Edge Pixels Lens Shift Pixels from Center of Pixel Array Bottom Edge (Center of P2S1) TEM of Transfer Gate (T1 or T2, Section B) TEM of Left Edge of Transfer Gate (T1 or T2, Section B)

8 Overview TEM of Transfer Gate Oxide (Section B) TEM of Source Follower Gate (T4, Section A) Source Follower Gate Silicon Etch (T4, Section A) Reset Gate TEM (T3, Section C) Reset Gate Silicon Etch SEM (T3, Section C) Radius of Curvature of Green Color Filter Radius of Curvature of Microlens Under Green Color Filter Blue Color Filter Red Color Filter Lens Buffer and Microlens Dark Pixel Overview Dark Pixels To Active Pixels Transition Transfer Transistors Gate Width (T1, T2, Section D) SCM of Cathode (Section D) Reset Transistor Gate Width (T3, Section E) Source Follower Transistor Gate Width (T4, Section F) 5 Memory Cell Analysis T SRAM Schematic T SRAM at Metal T SRAM at Metal T SRAM at Metal T SRAM at Poly T SRAM at Diffusion

9 Overview List of Tables 1 Overview Device Identification OmniVision BSI Technology Comparison OV8830 Device Summary OV8830 Process Summary 2 Device Overview Die Utilization 3 Process Analysis Substrate and Well Vertical Dimensions Shallow Trench Isolation Critical Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Measured Dielectric Thicknesses Front Metallization Thicknesses Front Metallization Width and Pitch Via and Contact Dimensions Back Dielectric and Metal Vertical Dimensions 4 Pixel Analysis Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions 6 Critical Dimensions Substrate and Well Vertical Dimensions Shallow Trench Isolation Critical Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Measured Dielectric Thicknesses Front Metallization Thicknesses Front Metallization Width and Pitch Via and Contact Dimensions Back Dielectric and Metal Vertical Dimensions Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions

10 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 3685 Richmond Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

Apple/AuthenTec TMDR92 iphone 5s, 6, and 6 Plus Fingerprint Sensor

Apple/AuthenTec TMDR92 iphone 5s, 6, and 6 Plus Fingerprint Sensor 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 www.chipworks.com Some of the information in this report may