HA MHz, High Slew Rate, High Output Current Buffer. Features. Applications. Ordering Information

Transcription

1 HA-5002 Data Sheet FN MHz, High Slew Rate, High Output Current Buffer The HA-5002 is a monolithic, wideband, high slew rate, high output current, buffer amplifier. Utilizing the advantages of the Intersil D.I. technologies, the HA-5002 current buffer offers 1300V/µs slew rate with 110MHz of bandwidth. The ±200mA output current capability is enhanced by a 3Ω output impedance. The monolithic HA-5002 will replace the hybrid LH0002 with corresponding performance increases. These characteristics range from the 3000kΩ input impedance to the increased output voltage swing. Monolithic design technologies have allowed a more precise buffer to be developed with more than an order of magnitude smaller gain error. The HA-5002 will provide many present hybrid users with a higher degree of reliability and at the same time increase overall circuit performance. For the military grade product, refer to the HA-5002/883 datasheet. Features Voltage Gain High Input Impedance kΩ Low Output Impedance Ω Very High Slew Rate V/µs Very Wide Bandwidth MHz High Output Current ±200mA Pulsed Output Current mA Monolithic Construction Pb-Free Plus Anneal Available (RoHS Compliant) Applications Line Driver Data Acquistion 110MHz Buffer Radara Cable Driver High Power Current Booster High Power Current Source Sample and Holds Video Products Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # HA HA to Pin Metal Can T8.C HA HA to 75 8 Pin Metal Can T8.C HA HA to 75 8 Ld PDIP E8.3 HA Z (Note) HA Z 0 to 75 8 Ld PDIP* (Pb-free) E8.3 HA4P HA4P to Ld PLCC N20.35 HA4P5002-5Z (Note) HA4P5002-5Z 0 to Ld PLCC (Pb-free) N20.35 HA9P to 75 8 Ld SOIC M8.15 HA9P5002-5Z (Note) 50025Z 0 to 75 8 Ld SOIC (Pb-free) M8.15 HA9P to 85 8 Ld SOIC M8.15 HA9P5002-9Z (Note) 50029Z -40 to 85 8 Ld SOIC (Pb-free) M8.15 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

2 Pinouts HA-5002 (PDIP, SOIC) TOP VIEW HA-5002 (PLCC) TOP VIEW HA-5002 (METAL CAN) TOP VIEW V 1 + V OUT V 2 + V V 1 + OUT V 2 + V 1 + V IN 4 5 V NOTE: Case Voltage = Floating IN V 1-1 IN 8 7 V 1-6 V OUT 2 FN

3 Absolute Maximum Ratings Voltage Between V+ and V- Terminals V Input Voltage V 1 + to V 1 - Output Current (Continuous) ±200mA Output Current (50ms On, 1s Off) ±400mA Operating Conditions Temperature Range HA C to 125 C HA C to 75 C HA C to 85 C Thermal Information Thermal Resistance (Typical, Note 2) θ JA ( C/W) θ JC ( C/W) PDIP Package* N/A Metal Can Package PLCC Package N/A SOIC Package N/A Max Junction Temperature (Hermetic Packages, Note 1) C Max Junction Temperature (Plastic Packages, Note 1) C Max Storage Temperature Range C to 150 C Max Lead Temperature (Soldering 10s) C (PLCC and SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175 C for the can packages, and below 150 C for the plastic packages. 2. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = ±12V to ±15V, R S = 50Ω, R L = 1kΩ, C L = 10pF, Unless Otherwise Specified TEST TEMP HA HA , -9 PARAMETER CONDITIONS ( C) MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage mv Full mv Average Offset Voltage Drift Full µv/ C Bias Current µa Full µa Input Resistance Full MΩ Input Noise Voltage 10Hz-1MHz µv P-P TRANSFER CHARACTERISTICS Voltage Gain R L = 50Ω V/V (V OUT = ±10V) R L = 100Ω V/V R L = 1kΩ V/V R L = 1kΩ Full V/V -3dB Bandwidth V IN = 1V P-P MHz AC Current Gain A/mA OUTPUT CHARACTERISTICS Output Voltage Swing R L = 100Ω 25 ±10 ± ±10 ± V R L = 1kΩ, V S = ±15V Full ±10 ± ±10 ± V R L = 1kΩ, V S = ±12V Full ±10 ± ±10 ± V Output Current V IN = ±10V, R L = 40Ω ma Output Resistance Full Ω Harmonic Distortion V IN = 1V RMS, f = 10kHz 25 - < < % TRANSIENT RESPONSE Full Power Bandwidth (Note 3) MHz Rise Time ns Propagation Delay ns Overshoot % Slew Rate V/ns Settling Time To 0.1% ns 3 FN

4 Electrical Specifications V SUPPLY = ±12V to ±15V, R S = 50Ω, R L = 1kΩ, C L = 10pF, Unless Otherwise Specified (Continued) TEST TEMP HA HA , -9 PARAMETER CONDITIONS ( C) MIN TYP MAX MIN TYP MAX UNITS Differential Gain R L = 500Ω % Differential Phase R L = 500Ω Degrees POWER REQUIREMENTS Supply Current ma Full ma Power Supply Rejection Ratio A V = 10V Full db NOTE: 3. Slew Rate FPBW = ;V. 2πV P =10V PEAK Test Circuit and Waveforms IN V 1 + R S +15V V 2 + OUT V 1 - V V R L FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE V IN V IN V OUT V OUT R S = 50Ω, R L = 100Ω SMALL SIGNAL WAVEFORMS R S = 50Ω, R L = 1kΩ SMALL SIGNAL WAVEFORMS 4 FN

5 Q 15 Q 23 HA-5002 Test Circuit and Waveforms (Continued) V IN V IN V OUT V OUT R S = 50Ω, R L = 100Ω LARGE SIGNAL WAVEFORMS R S = 50Ω, R L = 1kΩ LARGE SIGNAL WAVEFORMS Schematic Diagram V 1 + R 9 R 8 R N1 Q 19 R 4 R 1 V 2 + R 10 Q 25 Q Q Q 18 Q 3 Q 12 Q 9 Q 27 Q 6 Q 1 Q 10 R 5 IN Q 7 Q 4 R 11 OUT Q 21 R N2 Q 5 Q 11 Q 22 Q 2 Q 8 R 7 Q 24 R Q 6 17 Q Q Q 14 V 2 - R 12 R 3 R 2 R N3 V 1 - Application Information Layout Considerations The wide bandwidth of the HA-5002 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. Power Supply Decoupling For optimal device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from 0.01 to 0.1µF will minimize high frequency variations in supply voltage, while low frequency bypassing requires 5 FN

6 larger valued capacitors since the impedance of the capacitor is dependent on frequency. It is also recommended that the bypass capacitors be connected close to the HA-5002 (preferably directly to the supply pins). Operation at Reduced Supply Levels The HA-5002 can operate at supply voltage levels as low as ±5V and lower. Output swing is directly affected as well as slight reductions in slew rate and bandwidth. Short Circuit Protection The output current can be limited by using the following circuit: R V+ LIM = = I OUTMAX V I OUTMAX V+ I OUTMAX = 200mA (CONTINUOUS) Capacitive Loading The HA-5002 will drive large capacitive loads without oscillation but peak current limits should not be exceeded. Following the formula I = Cdv/dt implies that the slew rate or the capacitive load must be controlled to keep peak current below the maximum or use the current limiting approach as shown. The HA-5002 can become unstable with small capacitive loads (50pF) if certain precautions are not taken. Stability is enhanced by any one of the following: a source resistance in series with the input of 50Ω to 1kΩ; increasing capacitive load to 150pF or greater; decreasing C LOAD to 20pF or less; adding an output resistor of 10Ω to 50Ω; or adding feedback capacitance of 50pF or greater. Adding source resistance generally yields the best results. IN V 1 + V 1 - R LIM V 2 + V 2 - R LIM OUT V- 1.8 MAXIMUM POWER DISSIPATION (W) CAN PDIP SOIC PLCC QUIESCENT POWER DISSIPATION AT ±15V SUPPLIES TEMPERATURE ( C) T P JMAX T A DMAX = θ JC + θ CS + θ SA Where: T JMAX = Maximum Junction Temperature of the Device T A = Ambient θ JC = Junction to Case Thermal Resistance θ CS = Case to Heat Sink Thermal Resistance θ SA = Heat Sink to Ambient Thermal Resistance Graph is based on: T P JMAX T A DMAX = θ JA FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE 6 FN

7 Typical Application +12V V 1 + V 2 + R S R M RG -58 V IN V IN 50Ω V 1 - V V 50Ω V OUT R L 50Ω V OUT FIGURE 3. COAXIAL CABLE DRIVER - 50Ω SYSTEM Typical Performance Curves 9 6 V S = ±15V, R S = 50Ω 9 6 V S = ±15V, R S = 50Ω VOLTAGE GAIN (db) GAIN PHASE PHASE SHIFT VOLTAGE GAIN (db) GAIN PHASE PHASE SHIFT FREQUEY (MHz) FREQUEY (MHz) 180 FIGURE 4. GAIN/PHASE vs FREQUEY (R L = 1kΩ) FIGURE 5. GAIN/PHASE vs FREQUEY (R L = 50Ω) VOLTAGE GAIN (V/V) V S = ±15V V OUT = -10V TO +10V VOLTAGE GAIN (V/V) V S = ±15V V OUT = 0 TO +10V V OUT = 0 TO -10V TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 6. VOLTAGE GAIN vs TEMPERATURE (R L = 100Ω) FIGURE 7. VOLTAGE GAIN vs TEMPERATURE (R L = 1kΩ) 7 FN

8 Typical Performance Curves (Continued) OFFSET VOLTAGE (mv) V S = ±15V TEMPERATURE ( C) BIAS CURRENT (µa) V S = ±15V TEMPERATURE ( C) FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE FIGURE 9. BIAS CURRENT vs TEMPERATURE 15 V S = ±15V, R LOAD = 100Ω 10 9 V S = ±15V, I OUT = 0mA OUTPUT VOLTAGE (V) V OUT -V OUT SUPPLY CURRENT (ma) TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 10. MAXIMUM OUTPUT VOLTAGE vs TEMPERATURE FIGURE 11. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT (ma) I OUT = 0mA 125 C, 25 C -55 C IMPEDAE (Ω) 100K 10K V S = ±15V Z IN Z OUT SUPPLY VOLTAGE (±V) FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE 1 100K 1M 10M 100M FREQUEY (Hz) FIGURE 13. INPUT/OUTPUT IMPEDAE vs FREQUEY 8 FN

9 Typical Performance Curves (Continued) V OUT MAX, V P-P AT 100kHz T A = 125 C, T A = -55 C T A = 25 C R LOAD = 100Ω SUPPLY VOLTAGE (±V) PSRR (db) K 100K 1M 10M FREQUEY (Hz) 100M FIGURE 14. V OUT MAXIMUM vs V SUPPLY FIGURE 15. PSRR vs FREQUEY R L = 100 V S = ±15V T A = 25 C SLEW RATE (V/µs) V OUT - V IN (mv) R L = 1K R L = SUPPLY VOLTAGE (±V) INPUT VOLTAGE (VOLTS) FIGURE 16. SLEW RATE vs SUPPLY VOLTAGE FIGURE 17. GAIN ERROR vs INPUT VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): V 1 - TRANSISTOR COUNT: 27 PROCESS: Bipolar Dielectric Isolation 9 FN

10 Metallization Mask Layout HA-5002 V 1 - IN V 1 + (ALT) V 1 - (ALT) V 2 + V 2 - V 1 + OUT 10 FN

11 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D1 B1 -C- -A- N N/2 B D e D1 E1 -B- A (0.25) M C A A2 L B S NOTES: 1. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). A e C E C L e A C e B E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , 10 C D D E E e BSC 2.54 BSC - e A BSC 7.62 BSC 6 e B L N Rev. 0 12/93 11 FN

12 Metal Can Packages (Can) ØD ØD1 F Q A REFEREE PLANE Øb1 A A L L2 L1 Øb1 Øb ØD2 NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and from the reference plane. Diameter is uncontrolled in L1 and beyond from the reference plane. 2. Measured from maximum diameter of the product. 3. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M Controlling dimension: IH. Øe BASE AND SEATING PLANE BASE METAL SECTION A-A Øb2 2 β e1 LEAD FINISH 1 N α k k1 C L T8.C MIL-STD-1835 MACY1-X8 (A1) 8 LEAD METAL CAN PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A Øb Øb Øb ØD ØD ØD e BSC 5.08 BSC - e BSC 2.54 BSC - F k k L L L Q α 45 o BSC 45 o BSC 3 β 45 o BSC 45 o BSC 3 N Rev. 0 5/18/94 12 FN

13 Plastic Leaded Chip Carrier Packages (PLCC) (1.07) (1.22) PIN (1) IDENTIFIER D1 D (0.51) MAX 3 PLCS (0.66) (0.81) C L (1.07) (1.42) (1.27) TP E1 E C L A1 A (0.33) (0.53) (0.10) C (0.64) (1.14) R D2/E2 D2/E2 VIEW A (0.51) MIN SEATING PLANE N20.35 (JEDEC MS-018AA ISSUE A) 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A D D D , 5 E E E , 5 N Rev. 2 11/ (1.14) MIN VIEW A TYP (0.64) MIN -C- NOTES: 1. Controlling dimension: IH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. N is the number of terminal positions. 13 FN

14 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.25(0.010) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.25(0.010) M B A1 α 0.10(0.004) L M h x 45 NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e BSC 1.27 BSC - H h L N α Rev. 1 6/05 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 14 FN