An On-chip, 100-GHz Sampling Rate, 8-channel Sampling Oscilloscope Macro with Embedded Sampling Clock Generator

Transcription

1 An On-chip, 100-GHz Sampling Rate, 8-channel Sampling Oscilloscope Macro with Embedded Sampling Clock Generator M. Takamiya, M. Mizuno, and K. Nakamura NEC

2 Outline Background Sampling Oscilloscope Macro Sampling Head (SH) Sampling Clock Generator (SCG) Experimental Results Summary

3 Gnd Package Background Signal integrity degradation is critical with technology-scaling Supply noise, Substrate noise, Crosstalk,,, e.g.) di Supply Noise: V noise = L + Ri dt 0.8 L R ITRS 2001!? Vdd 0.6 MPU i 0.4 V noise V dd 0.2 Target LSI Year Simulation results are unreliable DIRECT measurement of on-chip waveforms is essential

4 On-chip Measurement Circuits On-chip waveforms are very fast (~several 10s ps) Off-chip Measurement? LSI Large Parasitic L, C Low Bandwidth 100 ps On-chip Measurement 10 ns Sampling Circuits LSI Time scale of outputs is expanded by sampling High Bandwidth On-chip sampling-type measurement circuits are needed

5 Proposed Macro Clk Sampling Clock Generator (SCG) SH Sampling Head (SH) SH Buffer Out LSI Objective: Checking signal integrity in LSI Design targets: (1) Embedded SCG for 100-GHz sampling with small area (2) SH with wide input range and high bandwidth (3) Simple measurement method

6 Advances over Past Work Block Diagram *smp: Sampling Clock Sampling Rate Input Range Measurement Method Comparator Past Work ISSCC 2000 VLSI 1998 smp Sampling Out (0111 ) ref Sampling Amp. Out smp This Work Sampling Amp. Out SCG smp Low (~10 GHz) High (100 GHz) Below Gnd ~ Above Vdd Gnd ~ Vdd Below Gnd ~ Above Vdd Complicated Simple Simpler

7 Outline Background Sampling Oscilloscope Macro Sampling Head (SH) Input Range Bandwidth Sampling Clock Generator (SCG) Experimental Results Summary

8 Sampling Oscilloscope Macro Clk T in N Vdd Gnd Substrate Clock Calibration Sampling Oscilloscope Macro Sampling Clock Generator (SCG) smpclk (T+ T) Sampling Head (SH) Selector xn 8 Signal Output Buffer out T x Oscilloscope 50 Ω Off-chip T T Multiple SH s share one SCG to save area Voltage and time-scale of the outputs need to be transformed

9 Sampling Head smpclk smpclk Sel Novel In Bias S3 S1 S2 S4 C1 C2 C3 Out Sample (20 ff) Precharge (70 ff) Hold (210 ff)

10 Input Range of Sampling Head V3 In Amp. Past Work (w/o C2) C1 C3 C1 C3 smpclk Amp. In This Work (with C2) BIAS C1 C2 C3 Amp. smpclk C1 C2 C3 V3 Amp. Vdd BIAS 0V In V3 (Conv.) V3 (This Work) Input Range of Amp. BIAS is set to the center of the input range of Amp. C2 achieves wide input range ( Vtn ~ Vdd+ Vtp )

11 Bandwidth of Sampling Head Relative Gain [db] w/o C2&S2,S3 2x Bandwidth Improvement 100M 1G 6.4G 10G Frequency [Hz] w/ C2&S2,S3 Bandwidth = 6.4 GHz The additional C2 & S2, S3 achieve 2X bandwidth by reducing the absolute gain

12 Outline Background Sampling Oscilloscope Macro Sampling Head (SH) Sampling Clock Generator (SCG) Sampling Operation Measurement Method Experimental Results Summary

13 Sampling Operation T 128T Clk Measured Signal Sampling Clock by SCG Out T+ T T 2 T 127 T Reset T Sampling Rate = T 1 Output time scale is scaled up T/ T times Output is only a portion of the input waveform

14 Time-Range and Area in SCG Narrow Range Wide Range Conv. Trade-off This Work Small Area Wide Range Offset-Delay Large Area Small Area Trade-off between time-range and area is resolved

15 Sampling Clock Generator Clk Offset-Delay Generator 1ns Selector T=10 ps 100-GHz Sampling Rate 0- to 7-ns delay by 1-ns step 0- to 1.27-ns delay by 10-ps step Fine-Delay Shifter 160ps Selector Phase Interpolator 40ps Selector Phase Interpolator 10ps Selector Sampling Clock

16 Measurement Method using SCG Original Input Waveform Calibrated Outputs (A) Selected by Offset- Delay Generator (B) (H) ns 1ns 1.27ns 8.27 ns Overlapping of 8 outputs by offset-delay generator expands time-range to 8.27 ns Overlap each waveform (A) (B) (C) (D) (E) (F) (G) (H)

17 Outline Background Sampling Oscilloscope Macro Sampling Head (SH) Sampling Clock Generator (SCG) Experimental Results Chip Micrograph DC Input vs. Output Clock Signal, Vdd/Gnd/Substrate Noise Summary

18 Chip Micrograph x4000 D Q SCG Activation Rate Controller 5-stage Noise Source 3.1 mm Eight SHs 2.1 mm

19 Chip Summary Technology Supply Voltage Sampling Osc. Macro Sampling Rate Frequency of SCG Decoupling Cap. Power Area SCG 23,600 µm 2 SH 1,550 µm 2 X 8 Noise-Source Power 0.13 µm CMOS, 6Cu 1.2 V 100 GHz < 800 MHz 910 pf 32 mw at 500 MHz < 1.1 W at 500 MHz

20 DC Calibration Output Voltage [V] Out of Supply Range Ground Voltage Supply Voltage Out of Supply Range DC Input Voltage [V] Wide Input range 0.3 V ~ Vdd V is demonstrated

21 Calibrated Voltage [V] With Decoupling Capacitors Without Decoupling Capacitors Clock Edge 10-ps Step Calibrated Time [ps] Experimental T=9.7ps Estimated bandwidth is ~8 GHz Decoupling cap. is essential Vdd1 Noise Source Gnd1 Vdd2 Samp. Osc. Gnd2

22 Calibrated Voltage [V] Demonstration of Overlapping Supply voltage noise (A) (A) (B) (C) (D) (B) (E) (F) Calibrated Time [ns] Overlapping 8 outputs expands time-range to 9 ns (G) (H) (C)

23 1.6 Supply and Ground Noise Calibrated Voltage [V] Supply Voltage Ground Voltage 100% 70% 40% 4.5 ns cycle 100% 70% 40% Activation Rate Calibrated Time [ns] SH captures both the overshoots and undershoots Off-chip Supply Voltage Off-chip Ground Voltage

24 Substrate and Ground Noise Calibrated Voltage [V] Substrate Voltage Ground Voltage Calibrated Time [ns]

25 Summary 8-channel Sampling Oscilloscope Macro contains: (1) Sampling clock generator for 100-GHz sampling with small area (2) Sampling head with wide input range and 8-GHz bandwidth (3) Decoupling cap. for noise-immune measurement 10 ps-step sampling measurements of supply/ground/substrate noise and clock signal have been demonstrated This macro is useful for checking signal integrity in LSIs

26 Backup for Q&A

27 Requirements On-chip measurement circuits for checking signal integrity require: (1) High Sampling Rate (~ 100 GHz) (2) Wide input range (below Gnd ~ above Vdd) (3) Simple measurement method Vdd several 10s ps Gnd Time

28 Voltage/Time-Scale Transformations Sampling Clock T+ T = 2.01 ns T x T T = 400 ns T = 2 ns Sampling Head Buffer Output Input LSI (1) Voltage (2) Time-Scale Out T 1 = T 200 In

29 How to Determine C1 & C2 in SH V IN V BIAS V3 Amp. V3 Amp. C1 C2 C3 smpclk C1 C2 C3 V high V BIAS V low Input Range of Amp. V IN V3 V3 = C1 x V IN + C2 x V BIAS C1 + C2 V low < V3 < V high

30 Why Delay-Line Design for SCG? 2-ns Cycle Sampling Clock Generator PLL or Delay-Line? Sampling Clk 2.01-ns Cycle clk Measured Circuits Sampling Head Sampling Rate Area Portability PLL Depends on Cycle Time Large Hard Delay-Line Constant Small Easy Time-range and area are trade-offs Offset-Delay Generator

31 Phase Interpolator 40 ps 20 ps 20 ps 10 ps 10 ps 10 ps 10 ps [1] JSSC, pp , [2] ISSCC, pp , 2001.

32 ESD-Tolerant Decoupling Cap. V dd Decoupling Capacitor Cell On High Low On Gate electrodes of MOSFETs are not connected with supply lines ESD-tolerant Gate capacitance of both nmos and pmos contributes to the decoupling via transistors Efficient use of area