This has become to be known as the stored program concept and is today the basis for virtually all computers in existence.

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1 3. : Data Flow We will develop, in some small amount of detail, the fundamental architectural concepts upon which all modern computers are built. As indicated in the above discussion, up until the mid-1940s computers were programmed by setting values using dials and switches and creating appropriate data paths by plugging cables into patch panels. In 1945 John Von Neumann proposed that the instructions to be executed can be written to the same memory where data resides and fetched using the same mechanisms used to fetch data. Thus, we can do away with all the switches and cables, store programs on magnetic media and just read them into storage when needed, and even write programs which could modify themselves (this last turns out not to be a good thing and modern programming languages are designed to discourage this practice.) This has become to be known as the stored program concept and is today the basis for virtually all computers in existence. The Fetch/Execution Cycle In order to develop the basic Von Neumann data flow we will start with the basic sequence of operations need to execute any instruction. Such a sequence involves five basic operations, and is known as the Fetch/Execute cycle 1. Fetch the instruction from memory 2. Decode the instruction and determine location of operands 3. Fetch the operands 4. Execute the instruction (perform the required operation) 5. Store the results 1. Instruction Fetch In order to be able to fetch an instruction from memory we need two things: a mechanism for communicating with storage, and a way to specify the location of the instruction to be executed. Memory is accessed by sending an address to the memory. Memory hardware controls will use the address to identify the location of the item being requested (in this case an instruction), retrieve it from the memory and send it back to the CPU. This leads to the requirement of an address bus which goes from the CPU to the memory over which the address can be sent, and a data bus from the memory to the CPU over which the data (instruction) will be returned. Whenever information is placed on a bus it must remain stable during the transfer time, so special purpose registers are used to hold the information during these transfers. In the CPU there is a Memory Address Register NTC 8/22/04 18

2 (MAR) into which the address is placed for as long as it takes the address to travel over the bus to memory. Also, a register is need to catch the data when it comes back from memory, and this is the Memory Data Register (MDR). This is all that is needed, at this point, for the purpose of fetching instructions from memory. Once the instruction is received over the memory data bus and stored in the MDR, it is passed to the register where it will be used (decoded), the Instruction Register (IR). But where did the address come from in the first place? It is a requirement in a Von Neumann machine that the instructions which constitute a program be stored sequentially in consecutive storage locations. Then all that is required in the CPU is a register which initially is set to point to the memory address of the first instruction. Thereafter, each time an instruction is fetched this register, called the Program Counter (PC), or sometimes the Instruction Pointer, (IP), is simply incremented to point to the next instruction in sequence. Therefore, to this point the data flow and its operation can be summarized as follows (assume the PC already contains the address of the next instruction to be executed): 1. The contents of the PC are passed to the MAR. This causes the address of the next instruction to be sent to the memory. 2. Increment the PC to point to the next instruction 3. The memory accesses the instruction identified by the contents of the MAR and places it on the data bus to the CPU 4. The instruction being fetched is loaded into the MDR from the memory data bus 5. The instruction is passed from the MDR to the IR 2. Instruction Decode With the instruction in the IR, hardware examines the Op Code to determine what operation is to be performed and whether any operands are required. If operands are required than the operand fields are used to determine the location of them. If we assume that the operands are also in storage, then the operand field contains the memory address of the operand. We therefore need a data path from the operand field of the IR to the MAR. How is the decode function performed? This is accomplished with circuitry which takes as inputs the m bits in the Op Code field of the instruction and produces as outputs 2 m individual signals, each of which corresponds to one of the combinations of 1's and 0's in the Op Code field. 3. Operand Fetch NTC 8/22/04 19

3 The operand address is passed over this bus whereupon it is sent to memory. Memory retrieves the operand and places it on the data bus, and subsequently it is loaded into the MDR. Once the MDR has been loaded with the operand it must move it to an Operand Register, or one of the GPRs, depending on the instruction. If this is an arithmetic instruction, for instance, the CPU could put the operand directly into one of the Operand Registers where it is immediately accessible by the ALU. If more than one operand is required the sequence described here is repeated until all operands have been acquired. 4. Execute With the operands in the appropriate operand registers, signals derived by decoding the Op Code field of the instruction in the IR are sent to the ALU, telling it which of the operations which it is capable of doing it should actually perform. The operands are then operated upon appropriately and the result is sent to the output of the ALU, where it might be placed in a dedicated Result Register or placed directly into a GPR 5. Store Results (Putaway) In addition to specifying operands, the instruction also specifies the location where the result, if any, is to be put away (stored). During this part of the fetch/execute cycle the output of the ALU (or the ALU Result Register) is placed in the designated location. Knowing the general sequence of operations (at the data flow level) we can now draw the data flow containing all the necessary components (so far as we understand at this time). NTC 8/22/04 20

4 Figure VN1. The boxes in the figure are the following components of the data flow: A Program Counter (PC)/Instruction Pointer (IP) B Memory Address Register (MAR) C Memory Data Register (MDR) D Instruction Register (IR) E, F Operand Registers G Arithmetic/Logic Unit (ALU) H ALU Result Register I General Purpose Registers (GPRs) J Instruction Decode logic NTC 8/22/04 21

5 Figure VN1 above is an example of a point-to-point data flow. It allows multiple things to occur simultaneously. For example, Updating the PC (PC PC+1) 4 Sending the PC contents to the MAR (MARPC) Sending GPR contents to the Operand Registers (ORAR1, ORBR3) Operating on the Operand Registers and putting the results in the Result Register. (RRORA + ORB) Putting the contents of the Result Register back into a GPR. (R2RR) All of these things (assuming multiple instructions are in progress at once) could all be done on the same cycle in the Diagram shown. Alternatively, a bus structure could be used as shown in Figure VN2 below. In this figure, any resource which needs the bus to transfer data must wait until the bus is free, since only one data item can occupy the bus at a time. 4 The expressions in parentheses (e.g. PC PC+1) are a shorthand way of specifying the operation being described, and are called micro-operations or micro-ops for short. We will use such expressions frequently from now on to specify such operations wherever necessary. NTC 8/22/04 22

6 Figure VN2 NTC 8/22/04 23

7 Review Questions 1. What are the five parts of the Fetch/Execute cycle? 2. Which parts of the Fetch/Execute cycle are required for every instruction? 3. What is the name of the concept which is John Von Neumann s contribution to Computer Architecture? 4. Which of the Registers in Figure VN1 is uniquely required by the Von Neumann Architecture (specifically by the requirement for instructions in consecutive storage locations.) 5. The following micro-ops are required for the execution of an ADD instruction: MAR PC PC PC+1 Memory MAR MDR Memory IR MDR OR A GPR 1 (OR A and OR B are Operand Registers) OR B GPR 2 RR OR A + OR B (RR is the result register) GPR 3 RR a. How many machine cycles will this take using the data flow in Figure VN1, assuming a one-cycle memory access time? b. How many machine cycles will this take using the data flow in Figure VN2, assuming a one-cycle memory access time? 6. What is the minimum number of cycles for the Fetch/Execute cycle (in Figure VN1), assuming that no operands are required (e. g. a branch instruction.)? 7. What is the maximum number of cycles for the Fetch/Execute cycle (in Figure VN1), assuming a single operand is required? NTC 8/22/04 24