von Neumann Model: Ch 4

Transcription

1 von Neumann Model: Ch 4 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 1

2 What is a computer? Introducing the von Neumann model John von Neumann ( ) proposed first storedprogram computer J. Presper Eckert and John Mauchly built the first storedprogram computer ENIAC in 1946 and EDVAC in Vijaykumar ECE495K Lecture Notes: Chapter 4 2

3 Elements of von Neumann model Processing Unit Performs arithmetic and logical operations Memory Indexed by address Stores data as content Also stores instructions (an instruction is a small unit of computation (e.g., add, subtract) for a given computer) Control Unit Interprets instructions and guides processing unit through program (sequence of instructions) Uses a finite state machine 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 3

4 More computer elements Input devices Feeds information into computer from external environment e.g., keyboard, scanner Output devices Conveys information from computer to environment e.g., monitor, printer Many devices are both e.g., network, disk, 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 4

5 Block diagram of von Neumann model MEMORY MAR MDR INPUT Keyboard Mouse Scanner Disk PROCESSING UNIT ALU TEMP OUTPUT Monitor Printer LED Disk CONTROL UNIT PC IR 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 5

6 Memory Unit Memory Address Register (MAR) Holds address of memory location being referenced Memory Data Register (MDR) On a read (or load), holds value from memory On a write (or store), holds value being written to memory Addressability how many bits are referenced by the minimum-granularity memory instruction Typically 8-bits today Address space how many locations can be addressed Addressing 2 n locations requires n address bits E.g., 2GB memory = 2 31 bytes => 31 address bits 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 6

7 Processing unit Simplest type is called Arithmetic/Logic Unit (ALU) Processing Unit also includes registers Small number of storage elements (small memory) Think of as temporary storage for intermediate results Indexed like a memory, but small number of locations (e.g., for most real processors whereas memory is 2GB) Why registers when there is memory? Smaller is faster So registers allow quicker access to intermediate results instead of going to memory 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 7

8 Processing unit Typical size of data inputs is called a word If ALU does 16-bit ADD, AND, OR, etc., then 16-bit word Most modern processors have 32-bit or 64-bit words Some embedded processors use 8-bit words Most computers also have FPU (floating-point unit) 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 8

9 Control Unit Makes all the other parts work together Uses a FSM (like our Traffic FSM but much bigger - many inputs/outputs - and more complicated) Program Counter (PC) Tells control unit which instruction to execute next Recall program is a sequence of instructions Holds address of next instruction (program is in memory) Normally, the next PC is the current PC plus one instruction Instruction Register (IR) Holds the instruction currently being executed Decoded to feed signals to other units and inputs to FSM 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 9

10 Types of instructions Computation Tells ALU to ADD, AND, SUBTRACT, etc. Typically take source operands from registers or IR and store result in a destination register Data movement Transfers information between memory and processing unit Control transfer Makes next PC be something other than current PC + 1 Conditional versus Unconditional changes of PC More on this in chapter Vijaykumar ECE495K Lecture Notes: Chapter 4 10

11 A Simple Program Program for e = (a+b)*c d Add a, b and put result in temp1 Multiply temp1, c and put result in temp2 Subtract temp2, d and put result in e add reg1 a + b (reg1 is temp1) mul reg2 reg1 * c (reg2 is temp2) sub e reg2 - d In LC3, add/mul/sub operate on data in registers but not directly on data in memory So a, b, c, d (and e) are first transferred to (from) registers using load/store instructions before add/mul/sub 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 11

12 A Simple Program Assume this program is stored in memory starting at addr 0x0 0x0 load reg3 0x100+0 (a is stored at 0x100) 0x1 load reg4 0x100+1 (b is stored at 0x101) 0x2 add reg1 reg3 + reg4 0x3 load reg5 0x100+2 (c is stored at 0x102) 0x4 mul reg2 reg1 * reg5 0x5 load reg6 0x100+3 (d is stored at 0x103) 0x6 sub reg7 reg2 reg6 0x7 store 0x100+4 reg7 (e is stored at 0x104) Example shows computation and data movement instructions Control transfer instructions later 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 12

13 A Simple Program How could I compute (2+3)*5 10 or ( )* ? How could I compute 845+(433*655) / 86? How could I make the computer send ? How could I make the computer open Facebook Web page? How could I make the computer print a report? All same hardware but different programs (software) Hence modern computers are programmable Hardware implements only the set of instructions and programs use different sequences of instructions to get their desired effect 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 13

14 A Simple Program Where is this program kept? What does it really look like? A bunch of 0s and 1s 0x0: x1: x2: x3: x4: x5: x6: x7: Vijaykumar ECE495K Lecture Notes: Chapter 4 14

15 How do programs run? Programs are usually too big to handle in one shot But programs are made of instructions So the hardware executes one instruction at a time But even one instruction is too big So hardware breaks up executing one instruction into many baby steps Hardware does one baby step at a time and goes to the next baby step Each baby step takes some action depending on the current instruction Next baby step depends on the current instruction Does this ring a bell? 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 15

16 Baby Steps for each instruction 1. Fetch instruction from memory Feed PC to MAR, read memory into MDR, copy into IR; increment PC for next instruction Instruction is represented by a series of 0s and 1s 2. Decode instruction Use combinational logic to figure out what instruction and 3. Evaluate memory address if needed 4. Fetch operands for computation Either from registers, memory unit, or IR itself 5. Execute instruction using operands 6. Store result into specified destination and go to step Vijaykumar ECE495K Lecture Notes: Chapter 4 16

17 Running the whole program Fetch load from 0x0, decode it, evaluate (x100+0), get its operands from 0x100, execute it (nothing!), store operand into reg3 Fetch load from 0x1, decode it, evaluate (x100+1), get its operands from 0x101, execute it (nothing!), store operand into reg4 Fetch add from 0x2, decode it, evaluate (not needed), get its operands from reg3 and reg4, execute it (add), store add result into reg1 Fetch load from 0x3, decode it, evaluate (x100+2), get its operands from 0x102, execute it (nothing!), store operand into reg5 Fetch mul from 0x4, decode it, evaluate (not needed), get its operands from reg1 and reg5, execute it (mul), store mul result into reg2 and so on., Vijaykumar ECE495K Lecture Notes: Chapter 4 17

18 Note about instruction processing Fetch, decode, eval, operands, exec,store, fetch, decode... The set of baby steps is sometimes called instruction cycle Not to be confused with clock cycle Each previous step may take one or more clock cycles Actual processors typically do things differently to optimize speed and power but the steps are essentially same Sequence of baby steps implemented through FSM Complex set of inputs and outputs E.g., states could be fetch1, fetch2, decode1, decode2, decode3, ev-addr1, ev-addr2, operand1, operand2, execute1, execute2, execute3, store-result Vijaykumar ECE495K Lecture Notes: Chapter 4 18

19 What do instructions do? It depends on the specific computer. Each computer has an instruction set to specify computation, data transfer, and control transfer tasks. Read pages Vijaykumar ECE495K Lecture Notes: Chapter 4 19

20 Where are we going from here? Ch 5 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 2009 Vijaykumar ECE495K Lecture Notes: Chapter 4 20