Advances in Applications and Ecosystem for FD-SOI technology

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1 Advances in Applications and Ecosystem for FD-SOI technology Kirk Ouellette Director of Marketing, Asia Digital Products Group STMicroelectronics Japan

2 Transistor 2 Bulk Gate Gate Source Drain Source Drain Ultra-Thin Buried oxide Substrate Punch Through! Substrate Typical Transistor in today CMOS System on Chip Change of Substrate adding the thin Buried oxide Improving power Efficiency Bringing high flexibility in SoC integration Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

3 28 FD-SOI vs. 28LP process 3 Process steps Same as 28LP 84% Adjusted from 28LP 14% FD-SOI specific 2% Very minimal change in process steps from the volume 28nm bulk transistor today while using less masks

4 UTBB FD-SOI, A Long R&D Story FD-SOI on Thin BOX Thin BOX (Buried OXide) wafers available from Soitec nm UTBB FD-SOI Available for production ST & LETI Module development & device understanding 2000, SON (Silicon On Nothing): an innovative process for advanced CMOS IEEE, TED, Nov Prized with the Rappaport Award for the best IEEE EDS paper of year , ST & LETI Fabrication of SON silicon 1997, CNET. Silicon On Nothing Fabrication of thin BOX on ordinary Bulk wafers within the CMOS process 1991, LETI. SmartCut patent 1992, Creation of SOITEC Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

5 SOC Performance Demonstration Today - 28nm FDSOI production available

6 Fully Depleted Transistors 6 FinFET FinFET & FD-SOI : Just a rotation ultimately converging when scaling BOX to TOX Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

7 addressing Power sensitive Markets 7 FinFet High end servers Networking Infrastructure Consumer Multimedia Internet of Things, wearables Laptops & tablet-pc Smartphone Automotive Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

8 FD-SOI Application Benefits Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

9 Application Benefits 9 Consumer Optimized SoC integration (Mixed-signal & RF) Energy efficient SoC in all thermal conditions Optimized leakage in idle mode Infrastructure Networking Energy efficient multicore Effective DVFS Excellent performance on memories Internet of Things Ultra-low voltage operation Highly Scalable operation Efficient RF and analog integration Automotive Well-managed leakage in high temperature environment High reliability thanks to highly-efficient memories Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

10 Network Infrastructure 10 Enterprise & Cloud Datacenter Core Network Access Network Backhaul Mobile Network Radio Access Network Performance and Power Efficiency Adapt power consumption to load Low SER enables simpler TCAM designs

11 Always On Cumulative Energy Efficiency 11 Energy Gain of FD-SOI 28nm versus 28G(mobile) for a given CPU usage profile Fraction of Time (CPU Usage) Device load usage profile example Wide DVFS combined with FD-SOI Scalability CPU Speed (MHz) CPU Speed usage Cumulated energy: 28G(mobile) 28FD-SOI Cumulative power lower with FDSOI : up to 70% better energy consumption vs bulk Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

12 Benefits for the IoT 12 Smart Car Smart Home Healthcare wellness Smart City Smart Industrial Ultra low voltage Low cost Easy integration of RF, connectivity, microcontrollers and power management Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

13 Example: Ultra Low Power in IoT 13 FSDOI - SoC 34 mw* Power Supply Loss SoC Power Consumption RF Analytics RF CPU & Memories Analytics Power Management CPU & Memories <10 mw* <5 mw** Other 40LP FD-SOI 28nm FD-SOI 14nm X3 to X6 Power Consumption Improvement with FD-SOI Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015 * Measured on Silicon / Product Simulation ** Projection

14 Benefits for Automotive 14 Challenges High ambient temperature = Limited budget for dynamic power dissipation FDSOI solution High performance at low voltage & power levels Managing leakage in high ambient temperature environments (Tj) Advanced DVFS and Scaling techniques CPU architecture advantages High reliability & safety critical requirements Excellent reliability and soft-error performance Lowers cost to achieve ASIL compliance interfaces Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

15 Video Analytics Processor for Automotive 15 FDSOI - SoC Camera Processing Embedded Memory FD-SOI Soft Error Rate (SER) allows for less overhead in memories for error correction SoC Power Consumption 5 W Quad Core CPU Video Analytics Processing 4 W 3 W Strict Safety Criteria met without systematic Usage of lockstep CPU operation Less use of redundant standard cell Due to lower SER Bulk 28nm Full lockstep CPU FD-SOI 28nm FD-SOI 28nm Full lockstep Optimized safety CPU architecture Power limit for mounted video analytics systems in a car ~3W Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

16 Roadmap 16 10nm +35% speed -50% power FD-SOI 14nm Derivativ Derivatives es Body Bias, simplicity, reliability FD-SOI 28nm RF, Mixed Signal Ultra Low voltage Embedded Non Volatile High Density & perf RAM Additional 28nm options continuing differentiation leadership

17 FD-SOI Technology Scalability Benefits in Analog Integration Radiation Immunity (SER) Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

18 How to Improve Energy Efficiency? 18 Several techniques exists but bulk process (28/14nm) are limited Technique Wide range DVFS Dynamic transistor Vt control Poly biasing of the transistors Limitations in Bulk [Vmin, Vmax] range is limited by variability Performance degradation when supply V reduces Memory Array minimum voltage Limited body bias range Limited benefit in 28 nm / no benefit beyond Limited poly biasing range New process & design technics are needed Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

19 allowing Ultra-Wide DVFS 19 FD-SOI allows the widest V dd range for voltage scaling 3 CPU freq. (GHz) 2.3 GHz at 1.0V 3.0 GHz at 1.34V 2 Still guaranteeing top notch speeds at very low operating voltage >5x when compared to 28LP HKMG technology >35% when compared to 28G technologies 1 1 GHz at 0.61V 300 MHz at 0.5V DVFS energy efficiency optimization is further extended by body biasing CPU supply (V) Real measurements of continuous DVFS in the range 0.5V 1.4V Performed on a very large number of ICs, showing extremely good reliability of the DVFS in this range

20 FD-SOI: The FBB advantage 20 What is Body Biasing? A voltage is applied to the substrate (or body). When voltage is positive, it is called Forward Body Biasing, or FBB Why FBB is much more efficient in FD-SOI? The Insulator layer (UTTB) prevents the parasitic effects that normally appear during the body biasing This allows much wider range of biasing compared to Bulk FBB can be modulated dynamically during the transistor operation and the transitions are transparent to the SW FBB benefits Performance boost Reduce power consumption at a given performance requirement Process compensation reducing the margins to be taken at design Easy to implement: seamless inclusion in the EDA flow Bulk FD-SOI 0 0.3V 0 1.3V Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

21 FBB provides performance boost when over voltage is not possible Limited impact on dynamic power, no impact on voltage drops More efficient than tuning the voltage FBB for performance boost and power efficiency Total Power 0.6V 1.1V FBB 1.1V 21 FBB Frequency FBB = more performance FBB improves the power efficiency at a given frequency Total Power Limited impact on leakage, slightly higher than without FBB Drastically decrease dynamic power FBB FBB = less power 0.6V 0.9V 0.8V 0.9V Frequency Easy to implement: seamless inclusion in the EDA flow Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

22 Power (log) FD-SOI vs. Bulk LP (HKMG) Speed/Leakage at 28nm 22 LP LVT PB4 PB10 PB0 +43% Perf. FD-SOI LVT PB4 w/o FBB PB0 FBB 600mV FBB 1.2V LP PB10 1/5 Power PB10 RVT FD-SOI RVT PB16 Operating Frequency (linear) FD-SOI enables Higher Performance, Lower Power and Dynamic Flexibility

23 FBB-based Process Compensation: Principle Typical FBB 23 FBB (to accelerate Slow parts) FBB (to reduce leakage on Fast parts) SS SS FF Frequency gain on Slow parts TT TT Fast parts leakage unchanged SLVT doesn t allow RBB FBB must be applied on typical to allow pseudo-rbb for Fast parts (leakage containment) Higher FBB is applied to accelerate Slow parts Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

24 Simpler Analog Integration 24 28FDSOI makes high-speed analog designer s life easier Everything is faster (analog switches / fast logic / regenerative comparator & latches) speed is higher then bulk technology Higher Gain and lower noise enable smaller ADC designs In High Speed ADC design, gain in speed versus Bulk: 50% gain, just using LVT and FBB NMOS porting from bulk 100% with redesign (NMOS oriented) Figure of merit better than FinFET technology thanks to lower intrinsic parasitic capacitance.

25 Best SER (Soft Error Rate) with 25 Experimental Failure-in-Time (FIT) test data Neutron-SER in FT/Mb ST, Roche IEDM 13 IRPS 14 NSREC 14 28nm FD-SOI Gain w.r.t. BULK UTBB FD-SOI FinFET Alpha Neutron Latchup immune not reported Multiple Cell Upsets 99% single bit max. 2 cells max. 4 cells worse according to INTEL ST, Roche, CISCO SER workshop, Oct 14 TSMC, Fang, CISCO SER workshop, Oct 14 ECC not mandatory High Latch-up Immunity Larger Integrated Memory Possible Rad-hard designs simpler FD-SOI provides a more reliable platform for mission critical operation Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

26 Ecosystem available in the whole chain 26 Wafer suppliers Design solutions Silicon manufacturing Several SOI wafers suppliers IP porting EDA Suppliers Design flow Libraries Volume production at ST and Samsung facilities

27 Fast Growing Ecosystem 27 Ecosystem Products Services IPs Tools & EDA Wafer & Foundry Enabling Consumer, Mobile, Networking and Automotive markets today

28 Example - Design Center Model Innovators Design Center Innovative pre-series INDUSTRY SME Specs MENTORING EXPERTISE DESIGN PLATFORM ACCESS TO MPW EMULATOR & TEST Prototype START-UP Competence partners Labs & Academia Industrial platforms Small, medium volume SKILLS INNOVATION IP, SILICON Chain value A single partner along product maturation

29 Complete Design Solution Available 29 Complete & flexible offering to match your technical and business requirements IPs Design Tools & Methodologies SerDes Multimedia CAD kits CPU GPU Interfaces Design Factory System Foundations Si Validation & Qualification Technology & Manufacturing

30 Extended FDSOI IP offer 30 Market Specific Networking Infrastructure Consumer Multimedia Automotive Mobile Consumer SerDes HDMI, DP MIPI, ISP TCAM Multimedia (Video Dec., Enc., Display) Advanced ARM CPU Subsystem GPU High Speed Interfaces DDR Interfaces DSP Security Foundations Standard Cells Memories System & Process Analog

31 Foundation IP offer 31 Market Specific Advanced 8T / 12T RVT /LVT Networking Poly bias: Infrastructure 0,4,10,16nm Low SerDes power: Isolation, Level shifters TCAM ARM CPU Subsystem Low voltage Single port / Dual port Consumer ROM Multimedia Process monitoring Metal ECO 4Tune Automotive PLLs, V/T sensors, eswitch Mobile Consumer ADC / DAC Ultra-high Sensors Voltage speed SRAM (process, HDMI, DP MIPI, ISP regulators thermal, voltage) Vbias Antifuse Oscillators generators memories Multimedia (Video Dec., Enc., Display) Frequency IOs synthesizer High Speed GPU Interfaces DDR Interfaces DSP Security Foundations Standard Cells Memories System & Process Analog

32 Advanced IP offer 32 Market Specific 32bit Cortex R4 Cortex A7 Cortex A9 Networking Cortex A15 Infrastructure 64bit Cortex SerDes A53 CorteA57 TCAM ARM MALI Imagination ROGUE Consumer Multimedia HDMI, DP Automotive USB2, USB3 PCIe SATA Ethernet Multimedia (Video Dec., Enc., Display) Mobile Consumer MIPI, ISP Advanced ARM CPU Subsystem GPU High Speed Interfaces Foundation DDR Interfaces DDR2/3 DDR3/4 s Standard Cells Memories LPDDR3 DSP XP70 32b System & Process Security Crypto Acc. AES Analog Hash

33 Market Specific FDSOI IP offer 33 Market Specific Networking Infrastructure Consumer Multimedia Automotive Mobile Consumer SerDes HDMI, DP MIPI, ISP TCAM Multimedia (Video Dec., Enc., Display) Advanced ARM CPU Subsystem GPU High Speed Interfaces DDR Interfaces DSP Security Foundations Standard Cells Memories System & Process Analog

34 Conclusion 34 ST has over 18 active FDSOI projects across multiple applications New applications emerging Automotive, Networking, IoT Some key features benefiting new applications Performance vs. Power scalability Analog Integration gate Thin Silicon film The FDSOI Ecosystem is growing rapidly Production of FDSOI products in various applications starting this year ST is providing IP, Design and Manufacturing Services for the FDSOI Ecosystem Kirk Ouellette Tokyo SOI Meeting - Jan 23, 2015

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