TQP Application Note

Transcription

1 TQP Application Board TQP TABLE OF CONTENTS 1.0 Description 2.0 Product Block Diagram and Operation 3.0 Recommended Handset Schematic and Layout Considerations 3.1 DC Block Recommendations 3.2 Bypassing Recommendations 3.3 PC Board Layout 4.0 Pin Out Table 5.0 Application Board Information 6.0 Additional Supporting Data 7.0 DC to DC Performance 8.0 Additional Information 1.0 DESCRIPTION This document describes the demonstration board for the TQP Front-End Module (FEM) for IEEE802.11a/n /ac WLAN applications. It includes schematics, assembly drawings, Bill of Material (BOM) and board construction information. It also includes information on board losses and other information that could affect the performance of the TQP with regards to comparisons with the Data Sheet specifications. Test data for the individual boards is included as a separate document or on CD. For additi oal information and latest specifications, see our website: 1

2 2.0 Product Block Diagram and Operation Please note that the Product Block Diagram presented here is for reference and discussion purposes and may not reflect the most up to date version included in the data sheet. Please refer to the data sheet document from the TriQuint web page for the most up to date information. PAEN VC1 TX PA ANT RX LNA LNAEN VDet The TQP combines many of the discrete components required for WLAN transmit and receive chains into a single module. The module contains a Power Amplifier (PA), Low Noise Amplifier (LNA) with a switched bypass mode, RF Power Detector (VDet) and RF switch. The RF ports of the device are TX, ANT and RX. Each of these ports has been internally matched to 50 ohms. However, some external matching may be required at each of the RF ports to optimize the overall system performance due to mismatch between the TQP and the RF components following these ports. DC supplies and control signals for the PA are carried on 1, 2, and 3, VC1, PAEN, and LNAEN. The pins provide the primary DC power supply for both the PA and LNA. VC1 provides control for the 5GHz RX path, while PAEN and LNAEN enable operation of the PA and LNA, respectively. Finally, VDET provides an output voltage from an internal RF detector which is proportional to the RF output power of the PA itself. This detector provides feedback to the System-on-a-Chip (SoC) with the equivalent RF output power of PA to ensure the correct Pout is maintained during operation of the mobile device. In normal operation, TX is connected to the RF output of a SoC. The manufacturer s recommended matching network should be used so that the VSWR interaction between the TQP and the SoC is minimized. The ANT port is connected to the handset antenna. The RX port is connected to the RX input of the SoC. Again, some matching adjustment may be necessary to get optimum performance from the complete TX and RX chain. lines are connected directly to the main power supply (battery or battery power switch). The SoC provides VC1, PAEN, and LNAEN and monitors the VDet signal. Please refer to the TQP datasheet for further technical specifications. 2

3 3.0 Recommended Handset Level Schematic and Layout Considerations The recommended handset level schematic for the TQP is presented in this section. External DC blocking capacitor is required on the ANT port. Two bypass capacitors are required on 1 and two on 2/3. These bypass capacitors should be placed as close to the FEM as possible to reduce supply line inductance. Depending on end application requirements, this section is separated into two parts: With and without external DC-to-DC control Recommended Handset Level Schematic without DC-to-DC Converter Below you will find the standard handset level schematic which has all three DC supply pins (Pins 4, 10, and 11) connected to the same DC supply (). Note: The TQP data sheet specifications are based on this configuration. Handset Level Schematic (Without DC-to-DC Converter) VC1 LNAEN C5 3.0pF ANT RX 2 3 U C3 12.0pF C4 0.1uF 4 9 C2 0.1uF C1 1.0nF VDet TX PAEN 3

4 3.0.2 Recommended Handset Level Schematic with DC-to-DC Converter In the case where it is desired to achieve current savings during low RF output power conditions, the TQP can be biased through a DC-to-DC converter which is connected to pin10 and 11 as shown below. Pin 4 will still need to be connected to where the voltage range is specified in the datasheet by the parameter 1. VC1 LNAEN Handset Level Schematic (With DC-to-DC Converter) C5 3.0pF ANT RX 2 3 U C3 12.0pF C4 0.1uF DC_DC 4 9 C2 0.1uF C1 1.0nF VDet TX PAEN Section 7 presents EVM and current vs. Pout according to DC-to-DC bias voltage on pin10, 11. TQP can save ~100mA with DC-to-DC biasing in low power (0dBm to 10dBm Pout range). 4

5 3.1 DC Block Recommendations The Antenna RF port (ANT) requires a DC Blocking Capacitor as illustrated with C5 (3.0pF). All other RF ports (TX and RX) are internally DC blocked. 3.2 Bypassing Recommendations The supply voltage for the FEM is supplied externally through (or and DC_DC in the case of current savings during low power operation). Power supply bypassing on (and DC_DC if applicable) is accomplished by 4 surface mount capacitors (C1, C2, C3 and C4) which are placed as close to the FEM as possible. Note: For optimal phone level performance, the exact value of the RF bypass capacitor (C3) may need to be adjusted depending on PCB parasitics. Control voltages are supplied externally though VC1, PAEN, and LNAEN. These pins do not require bypass capacitors but adding provisions for debug purposes is recommended. Values of the capacitors on control supply lines can be changed to meet dynamic switching speed requirements during initial product development. 5

6 3.3 PC Board Layout RF Layout and Calibration Losses RF layout is critical in achieving the specified performance of the TQP Impedances of all the RF traces should be 50 Ω. When determining device performance at the package pins using a connectorized PC board, the RF trace losses need to be subtracted from the measured data (Section 6.2) Grounding Considerations Providing the FEM with proper grounding is required to ensure optimal performance. It is important to maintain a solid/uninterrupted ground beneath the FEM and ensure the ground vias connect to True Ground. Depending on the type of design, the location of True Ground can be different. Do not run signal traces or supply lines beneath the FEM ground. Below are high level descriptions of two different designs Module and Mobile Device PCB: Module Based Design In a Module Based Design, the WLAN System (FEM and SoC) is mounted on a separate PCB which is then mounted onto the final product (Mobile Device PCB). The FEM on the module will not see a True Ground until the ground vias make contact to the ground layer of the Mobile Device PCB as illustrated below. FEM Ground VIAs Bypass Caps and Ground Slug Uninterrupted Connection to Module Bottom Layer Module Mid Layer Ground Not a True Ground WiFi Radio Module PCB SoC FEM Module Bottom Layer Ground is Considered to be True Ground Connection Point to Mobile Device PCB Mobile Device PCB Mobile Device PCB Grounds Depending on Design - May be Middle layer or Bottom Layer Mobile Device PCB Design In a Mobile Device PCB Design, the WLAN System is mounted directly onto the final product (Mobile Device PCB). The FEM will see a True Ground when the ground vias connect to the Mobile Device PCB ground layer. FEM Ground VIAs Bypass Caps and Ground Slug Uninterrupted Connection to Mobile Device PCB Ground WiFi Radio Mounted Directly onto Mobile Device PCB SoC FEM Mobile Device PCB True Ground Depending on Design - May be Middle layer or Bottom Layer 6

7 3.3.3 Recommended Antenna Port Matching Configuration The TQP optimum load for EVM is presented at approximately (0.7~0.8-J0.2). Because the 5GHz WLAN band covers almost 1GHz of bandwidth (4900MHz to 5925MHz) and it can be very difficult to present this impedance over the entire bandwidth in the end application. TQS strongly recommends implementing a 4 element matching network as shown below to maximize tuning combinations. In addition, if external inductors are needed it is important to select high Q inductors due to the high frequency nature of this application. 7

8 3.3.4 Footprint Recommendations This section provides footprint information based on package dimensions. Detailed package dimensions can be found in the TQP Datasheet. Top Layer Metal Layer (in mm) / / / / Top Layer Solder Mask and Stencil (in mm) / / / (Square) / Solder Stencil: 100% Pad, 50% Ground Slug / Solder Mask 8

9 4.0 Pinout Table U Pin Description Function 1 GND Ground 2 RX 5GHz RX Output Pin 3 GND Ground 4 1 Supply Pin for 5GHz LNA, Switch, PA bias, and PA 1 st Stage 5 VDet Detector Pin for 5GHz PA 6 PA_EN 5GHz PA Enable and TX Switch Pin 7 GND Ground 8 TX 5GHz PA Input 9 Spare N/C or Ground 10 2 Supply Pin for 5GHz PA 2 nd Stage 11 3 Supply Pin for 5GHz PA 3 rd Stage 12 GND Ground 13 ANT 5GHz Antenna Pin 14 GND Ground 15 VC1 Control Pin for 5GHz RX 16 LNA_EN 5GHz LNA Enable Pin 17 GND Package Ground 9

10 5.0 Application Board Information The TriQuint Application board has been designed to provide performance as close as possible to the actual system level performance. Assembly drawings and layer stack up are included here to illustrate layout practices that will help ensure superior performance in a handset board application. Further assistance may be requested from TriQuint Application Engineering. 5.1 Application Board Schematic Vdd GND PA_EN LNA_EN PAEN LNAEN C1 4.7uF Vc1 VC1 Aux Aux GND Vdet VDet RX C4 C5 C6 0.1uF C7 1nF C8 LNAEN TX VDet C13 C10 R1 0ohm R2 0ohm C14 PAEN C11 Vdet PAEN GND TX GND RX GND U1 N/C GND LNAEN VC1 GND ANT L1 C9 C12 3.0pF VC1 L2 ANT AUX C19 C15 C16 C17 0.1uF C18 12pF Note: C8, C9, C10, and C11 can be populated to reduce the rise time if necessary. Also, AUX is not applicable to the TQP and can be left unconnected. 10

11 5.2 Applications Board Bill of Material (BOM) Component Reference Designator Value Size Quantity Part Number FEM U1 1 TQP Capacitor C1 4.7uF Capacitor C6, C17 0.1uF Capacitor C7 1nF Capacitor C18 12pF Capacitor C12 3pF Resistor R1, R2 0 Ohm Evaluation Board 5.8 GHz WLAN PA 1 Rev 3 11

12 5.3 Application Board Silkscreen and Top Assembly Drawing Silkscreen Top Assembly Drawing Note the Orientation of U1 C7 C6 C12 U1 TQP R1 R2 C18 C17 12

13 5.4 Applications Board Copper Layers and Board Construction Top Layer Internal Layers (Mid1 and Mid2) Mid 1 Layer (Ground Plane, Negative Layer) Mid 2 Layer ( and Ground Plane, Positive 13

14 Bottom Layer (Viewed Through Board from Top) 14

15 6.0 Additional Supporting Data 6.1 Truth Table for Various Modes 6.2 PC Board Offset 5GHz FEM VC1 LNA_EN PA_EN RX/LNAON RX/Bypass WLAN TX Shutdown The following are the offsets that can be used for the TriQuint application board as mentioned in section MEASUREMENT RX Insertion Loss TX Insertion Loss ANT Insertion Loss OFFSET 0.6dB 0.5dB 0.5dB 15

16 7.0 DC to DC Performance (5500MHz, 80MHz AC) IBatt (ma) vs. Pout (dbm) and DC_DC (V) EVM (db) vs. Pout (dbm) and DC_DC (V) 16

17 8.0 Additional Information For technical questions and application information: Please contact TriQuint Application Engineering Team Additional Information 1 1 For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: Tel: (503) info_wireless@tqs.com Fax: (503) For technical questions and additional information on specific applications: info_wireless@tqs.com The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright 2006 TriQuint Semiconductor, Inc. All rights reserved. 17