Multiple Laminations in Pb-free Project. HDPUG Meeting (China) Nov., 2012 Chair: Ivan Straznicky Curtiss-Wright Controls

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Elmer Greene
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1 Multiple Laminations in Pb-free Project HDPUG Meeting (China) Nov., 2012 Chair: Ivan Straznicky Curtiss-Wright Controls

2 Background As BGA pitch decreases and I/O count increases, stacked microvia designs become necessary. There is little data in the public domain on the reliability of stacked designs, and what does exist is concerning. OEM data shows that some stacked structures can be built reliably, but need to know what combination of structures, materials, and other parameters result in acceptable reliability.

3 Project Overview Evaluate the reliability of multi-stacked microvias in Pb-free Evaluate 2, 3, and 4 stack microvias both stand alone and stacked on buried via compared to through hole vias using IST (Interconnect Stress Testing) Three different thicknesses (.062,.093,.125) Stress location varies with thickness Maximum stresses vary with thickness Different materials (high, medium and low z-axis CTE) Z-axis CTE of materials affects stresses Simulated BGA pitches (0.8/0.4mm and 1.0/0.5mm) Pitch related to Pb-free survivability Precondition prior to IST cycling using 6X@ 260ºC reflow Screen materials for delam before committing to IST TMA/DMA/TGA testing to determine material properties and if/how they degrade during processing and preconditioning

4 Simplified Sketches of Via Structures Thru and SCV 1mm and 0.8mm pitch, MV 0.5 and 0.4mm pitch Microvia stack on BV Microvia stack/offset BV

5 Coupon design & fabrication Buried via size (10 mil drill, 20 mil pad, mil anti-pad) 0.5mm pitch microvia size (10 mil pad, 4-5 mil diameter) 0.4mm pitch microvia size (8 mil pad, 3-4 mil diameter) Single stripline stack-up (1/2 oz for signals, 1 oz for planes) Foil build with ¼ oz starting weight for plated layers RTF copper for cores Non-functional pads (NFPs) removed on every other signal layer Buried vias prefilled with non-conductive fill (e.g. San Ei PHP900)

6 IST Coupon/Panel Design 1 st coupon design created by PWB Interconnect (18 layer, 5 lam) shown below. Other coupon designs completed and being panelized. Coupon/panel designs will be sent to fabricators for review.

7 Material Selection Project considered low, medium and high CTEs (based on HDPUG data) Low CTE ~ ppm/c (<Tg) Med CTE ~ ppm/c (<Tg) High CTE >70 ppm/c (<Tg) Also took into consideration the following: HDPUG Phase 1 & 2 results OEM use and experience Fabricator experience (e.g. multiple lam) Laminate mfr input Want some high speed, low loss materials

8 Material Selection Z-axis CTE (HDP data, ppm/ C) Z-axis expansion Tg (datasheet, 50- (datasheet 260 C, %), C) Fabricator1 (Viasystems) recommendation Z-axis CTE Z-axis CTE (datasheet, Manufacturer Material Hi, Med, Lo ppm/ C) Panasonic R5725 (Meg 4) 40 L 35 * Rogers Theta 62(1) M 40 * Isola FR408HR 78(2) H 65 * Shengyi S1190 L * Hitachi MCL-E-75 M * Panasonic R1566V H 48 ~3 145 * (1) - this is data from Hitachi HE-679G (same resin system) (2) - this data from Same TV - but not done in HDP study L=40-55 (from HDP data, if no data use Z-axis expansion) M=55-70 (from HDP data, if no data use Z-axis expansion) H>70 (from HDP data, if no data use Z-axis expansion) Fabricator2 (TTM) recommendation

9 Characterization coupons TMA, TGA, DSC coupons will be ½ x ½ with at least 2X area keepout to mitigate high/low pressure lam issues. DMA coupon will be separate. TMA/TGA/DSC will be performed after each lamination (5 lam build only) and after each reflow (or every 2 nd reflow). Sacrificial panels will be built (5 lam build only), with one panel pulled after each lam DMA will be done after fabrication (all lams) and after each reflow (or maybe every 2 nd reflow). Requires up to 7 coupons (as received and 6 reflows) Coupon traceability will be critical Marking similar to high speed project approach (3-4 digits) Who does testing? Laminators have capability and have expressed willingness. PWB Interconnect has TMA and DMA capabilities.

10 Proposed Full Factorial DOE Cell Material Thickness Layers Build Offset BV, 1mm pitch Offset BV, 0.8mm pitch On BV, 1mm pitch On BV, 0.8mm pitch PTH, 1&0.8mm pitch # Panels 1 Low CTE lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD 10 Med CTE lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD 19 High CTE lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD lam 6 coupons 6 coupons 6 coupons 6 coupons 6 coupons TBD

11 Project Flowchart

12 Project Schedule Project Task Responsible Prelim Current Plan Project Ivan/others 3/31/2012 Ongoing Material selection Various 2/29/2012 Complete IST coupon/panel design PWBi 6/29/2012 Complete Design review Via & TTM 6/8/ /28/2012 Issue stack-ups Via & TTM 6/29/2012 Laminate supply Laminate mfrs 8/17/2012 Panel fabrication (incl. 6x288C test) Via & TTM 12/14/2012 IST coupon pre-screening PWBi 12/21/2012 Assembly preconditioning CW 1/18/2013 Capacitance screening PWBi 1/31/2013 MAT coupon testing PWBi 1/31/2013 IST test protocol confirmation PWBi/team 2/28/2013 IST coupon testing PWBi 3/31/2013 TMA/DMA/TGA coupon testing PWBi 3/31/2013 Failure Analysis (location & sectioning) PWBi, Via & TTM 5/31/2013 Test data analysis Various 6/30/2013 Publish report Ivan/others 8/31/2013

13 Questions This project evaluates a full balanced stack with equal micro vias on each side of the blind vias. What would happen if it was an unbalanced or partial stack? When do we reach the limits of plated vias? When Does Any Layer Via start?

14 Thank you Questions?

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