GPU Computing & Architectures 1. Introduction. Ezio Bartocci Vienna University of Technology

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1 GPU Computing & Architectures 1. Introduction Ezio Bartocci Vienna University of Technology

2 Objectives: Aim of this course Gaining understanding of GPU computing architecture Getting familiar with GPU programming environments Learning Compute Unified Device Architecture (CUDA) Implementing programs solving problems that would classically have been run on a supercomputer Requirements C/C++

3 Resources Website: Books CUDA by Example: An Introduction to General-Purpose GPU Programming Jason Sanders, Edward Kandrot, Addison Wesley Programming Massively Parallel Processors: A Hands-on Approach David B. Kirk, Wen-mei W. Hwu, Morgan Kaufmann GPU Computing GEMS Emerald Edition Wen-Mei w. Hwu, Morgan Kaufmann

4 Schedule of the course

5 Moore s Law 2,600,000,000 1,000,000, ,000,000 10,000,000 1,000, ,000 10,000 2, Gordon Moore, co- Founder Intel Corpora4on The number of the transistors of the integrated circuits double every 18 months

6 Moore s Law More transistors, but how to get them really fast? 2,600,000,000 1,000,000, ,000,000 10,000,000 1,000, ,000 10,000 2, Gordon Moore, co- Founder Intel Corpora4on The number of the transistors of the integrated circuits double every 18 months

7 Moore s Law More transistors, but how to get them really fast? 1 Increasing the processor speed i386 DX 1985 Sandy Bridge MHz 3.7 GHz Power ~ Freq3 Single Core 1 GHz / 1 Watt Single Core 4 GHz / 43=64 Watts 2 Increasing the parallelism (concurrency, multithreading) CPU Intel Xeon E5 v3 GPU NVIDIA TITAN Z Cores 5760 Cores Power ~ Num. of Cores Single Core 1 GHz / 1 Watt 4 Cores 1 GHz / 4 Watts

8 GPU vs CPU Graphic Processing Unit Central Processing Unit

9 GPU vs CPU Graphic Processing Unit Central Processing Unit

10 GPU vs CPU Graphic Processing Unit Central Processing Unit Chip Design ALU: Arithmetic Logic Unit GPU devotes more transistors to data processing

11 NVIDIA GPU Roadmap

12 NVIDIA Tesla Architecture MT Issue: Multithreaded instruction fetch TPCs: Texture/Processor Clusters SMs: Stream Multiprocessors SPs: Streaming Processors SFU: Special Function Unit (4 floating-point multipliers)

13 Single Instruction Multiple Data The GPU core is called stream processor Stream processors are grouped in Stream Multiprocessors SM is a SIMD processor It is also called Single Instruction Multiple Threads Instruction c = a + b Fetch/Decode Core Core Core a b c = Data

14 What about branches? Time (clocks) ALU1 ALU2 ALU8 If (x > 0) { y = x * x; y += 3; a = y + 3; } else { x = 0; a = 3; }

15 What about branches? Time (clocks) ALU1 ALU2 ALU8 T T F T F F F F If (x > 0) { y = x * x; y += 3; a = y + 3; } else { x = 0; a = 3; }

16 What about branches? Time (clocks) ALU1 ALU2 ALU8 T T F T F F F F If (x > 0) { y = x * x; y += 3; a = y + 3; } else { x = 0; a = 3; } Not all the ALUs do useful work! Worst case: 1/8 performance

17 NVIDIA Fermi Architecture

18 NVIDIA Fermi Architecture Each CUDA processor has a fully pipelined integer arithmetic logic unit (ALU) and floating point unit (FPU). More cores per multiprocessors and faster arithmetic operations Memory Protection Support: Memory are protected by a Single Error Correct Double Error Detect (SECDED) ECC code

19 GPU Design trend GPU are designed to host many simple cores: The cores are designed to performs very simple task: high throughput (number of tasks in a fixed time) They have few controls units: this may introduce latency (time to complete a task) Objectives of a good programmer are: Maximize throughput of all threads Minimize latency of a thread

20 Hiding latency A group of threads that want to access to the global memory or texture may introduce latency Time (clocks) Credits for the slide: M. Houston

21 Hiding latency A group of threads that want to access to the global memory or texture may introduce latency Time (clocks) Credits for the slide: M. Houston

22 Hiding latency A group of threads that want to access to the global memory or texture may introduce latency Time (clocks) Credits for the slide: M. Houston

23 Hiding latency A group of threads that want to access to the global memory or texture may introduce latency Time (clocks) Credits for the slide: M. Houston

24 Hiding latency A group of threads that want to access to the global memory or texture may introduce latency Time (clocks) Credits for the slide: M. Houston

25 Increasing High-throughput A group of threads that want to access to the global memory or texture may introduce latency Time (clocks) Credits for the slide: M. Houston

26 NVIDIA Kepler Architecture

27 NVIDIA Kepler Architecture

28 NVIDIA Kepler Architecture

29 NVIDIA Kepler Architecture

30 CUDA Computer Unified Device Architecture Parallel computer architecture developed by NVIDIA General purpose programming model: Offers a computed designed API Explicit GPU memory managing CUDA Plymouth by zede

31 GPU Computing Applications

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