Jin-Fu Li. Department of Electrical Engineering National Central University Jungli, Taiwan
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1 Chapter 4 Fault Simulation Jin-Fu Li Advanced d Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jungli, Taiwan
2 Outline Introduction Fault Simulation Parallel Fault Simulation Deductive Fault Simulation Concurrent Fault Simulation Summary Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
3 Simulation Definition Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator Simulator is used for design verification Validate assumptions Verify logic Verify performance (timing) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
4 Levels of Simulation System level Architecture level Functional level/rtl level Gate/structural t t levell Switch/transistor/circuit level Mixed level System level el RTL levelel Gate level el Reg A clk Reg B a b Adder c z Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
5 Simulation Process Stimuli Model Library Simulator Response Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
6 Modeling Modules, blocks or components described by Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gate, etc. Interconnects represent Ideal signal carriers or ideal electrical conductors Netlist A format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
7 Example: Full-Adder Netlists a b d HA e HA; c inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); f AND: A2,,(d, e), ),(); (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); A B C HA1 FA; D Carry inputs: A, B, C; E F outputs: Carry, Sum; HA2 Sum HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
8 Types of Simulation Compiled simulation Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for lowactivity circuits High-level (e.g., C language) models can be used Event-driven simulation Only gates or modules with input events are evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
9 Compiled Simulation Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flip-flops) Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) Execute compiled code Report or save computed variables Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
10 Event-Driven Simulation a =1 c = d = 0 e =1 2 g =1 1 Scheduled Activity events list 0 c = 0 d, e 2 d = 1, e = 0 f, g b =1 4 f =0 g Time, t Time stack 3 4 g = f = 1 g 7 8 g = 1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
11 Time Wheel (Circular Stack) Current time pointer max t= Event link-list Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
12 Efficiency of Event-Driven Simulator Simulates events (value changes) only Speed up over compiled-code code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change Steady 0 0 to 1 event Steady 0 Large logic block without (no event) activity Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
13 Fault Simulation Fault simulation In general, simulating a circuit in the presence of faults is known as fault simulation The main goals of fault simulation Measuring the effectiveness of the test patterns Guiding the test pattern generator program Generating fault dictionaries Outputs t of fault simulation Fault coverage - fraction (or percentage) of modeled d faults detected t d by test t vectors Set of undetected faults Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
14 Elements of Fault Simulation The fault simulation process is illustrated as below Fault List Test Set Design Model Library Fault Simulator Evaluation The fault simulator affects the speed of overall fault simulation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
15 Fault Simulation Scenario Circuit model: mixed-level Mostly logic with some switch-level for high- impedance (Z) and bidirectional signals Signal states: logic Two states (0, 1), three states (0, 1, X), four states (0, 1, X, Z), etc. Timing: Zero-delay For combinational circuits with no feedback Unit-delay It can maintain the proper sequencing of signal changes Multiple-delay Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
16 Fault Simulation Scenario Faults Mostly single stuck-at faults Sometimes stuck-open, transition, and pathdelay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault dropping -- a fault once detected is dropped d from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit cu is large Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
17 Serial Fault Simulation Serial fault simulation algorithm Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors Advantages Easy to implement; needs only a true-value simulator Less memory is required Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
18 Serial Fault Simulation Disadvantages Much repeated computation; CPU time prohibitive for VLSI circuits Alternative Simulate many faults together Test vectors Fault-free circuit Comparator f1 detected? Circuit with fault f1 Comparator f2 detected? Circuit with fault f2 Comparator fn detected? Circuit with fault fn Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
19 Parallel Fault Simulation Assumptions The simulated circuit consists of only logic gates and all gates have the same delays Signals take only binary (0 and 1) values Main idea Take advantage of the bit-parallelism of logical operations in a digital computer For a 32-bit machine word, an integer consists of a 32-bit binary vector A logic AND or OR operation involving two words performs simultaneous AND or OR operations on all respective pairs of bits Storage requirement One word per line for two-state simulation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
20 Speedup If the computer word size is N, then N-1 copies of faulty circuit are also generated For a total M faults in the circuit, M /( N 1) simulation runs are then necessary Speedup over serial fault simulation about N-1 Disadvantages Lacking the capability to simulate accurate rise and fall delays of signals Not suitable for circuits it with non-boolean logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
21 An Example of Parallel Fault Sim. Bit 0: fault-free free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1 a b c s-a-0 e c s-a-0 detected g d f s-a Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
22 Deductive Fault Simulation Simulating only the behavior of the fault- free logic circuits Need only one pass for each test pattern All signal values in each faulty circuit i are deduced from the fault-free circuit values and the circuit i structure For each test pattern, a deductive procedure is applied to all lines in a levelorder (for combinational logic) from inputs to outputs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
23 Deductive Fault Simulation Definition The fault list L A is defined as the set containing the name or index of every fault that produces an error on line A when the circuit is in its current logic state Fault lists are to be propagated from PIs to the POs A fault list is generated for each signal lines, and updated as necessary with every change in the logic state of the circuit List events occur when a fault list changes Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
24 An Example of Deductive Fault Sim Consider a 4-input NOR gate with input {ABCD}={0011}, { }, given the initial fault lists as show below A B C D E L A ={a,e} L B ={b,c} L C ={a,b,c,d} L D ={a,d,f}, The faults that propagate to E are those causing E to be complemented ' LE = ( LA LB ) LC LD = { α α LC LD & α LA LB} We also have to consider internal faults producing incorrect output for the current good input ' L = L { E /1} { d, E /1} E E = Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
25 Fault List Propagation Let I be the set of inputs of a gate with output Z, controlling value c, and inversion i. Let C be the set of inputs with value c. The fault list L Z is computed as follows: if ( C = φ ) then L = { L } { Z /( c i )}; Z j I j else L Z = ({ L j } { L j }) { Z /( c i )} j C j I C Controlling value: c= inversion: i= 0, for AND/NAND gates 1, for OR/NOR gates 0, for AND/OR gates 1, for NAND/NOR gates Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25
26 An Example of Deductive Fault Sim Notation: L k is fault list for line k k n is s-a-n fault on line k a b L {a/0} e = L a U L c U {e/0} 1 = {a/0, b/0, c/0, e/0} 1 {b/0, / c/0} } e 1 {b/0} c 1 g d f 0 {b/0, d/0} {b/0, d/0, f/1} L g = (L e L f ) U {g/0} = {a/0, c/0, e/0, g/0} U Faults detected by the input vector Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26
27 Concurrent Fault Simulation Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that t differ in signal states t from the faultfree circuit. A list per gate containing i copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. All events of fault-free and all faulty circuits are implicitly simulated Faster than other methods, but uses most memory. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
28 An Example of Concurrent Fault Sim a/0 b/0 c/0 e/0 a b 1 1 c d e 1 f g a/0 b/0 c/0 e/ b/0 d/0 f/ g/0 f/1 1 d/0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
29 Summary Fault simulator is an essential tool for test development The main goals of fault simulation Measuring the effectiveness of the test patterns Guiding the test pattern generator program Generating fault dictionaries Concurrent fault simulation algorithm offers the best choice Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29
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