Lecture 18. SRAM Cell and Column I/O Design

Transcription

1 Lecture 8 SRAM Cell nd Column I/O Design Res Sleh Dept. of ECE University of British Columi res@ece.uc.c Architecture of 64K SRAM Row decoder m =56 word line Column Pullups itline n=8 n =56 Address input m=8 Column decoder m Column Mux Red/Write Sense en Write en Red-write control Sense mplifier Write driver Dt In Dt Out

2 SRAM Storge Cell Uses six trnsistors (clled 6T memory ): wordline inverter inverter Single Stge Noise Mrgin V OL V S V OH Red nd write opertions use the sme port. There is one wordline nd two it lines. The it lines crry complementry dt, fct tht will e used to reduce ccess time. The lyout is smll since it hs smll numer of wires (ut lrge reltive to DRAM). 3 CMOS SRAM Cell Design w wp wd wp wd w Cell Design Prolem: Find w, wd, wp such tht ) minimize re ) otin good red nd write mrgins 3) good soft error immunity 4) good red current in tht order wp w Since the is symmetric we need only design three trnsistor sizes wd 4

3 CMOS SRAM design - red Mke sure tht internl node does not go high enough to turn on M Use threshold voltge s mximum lloe voltge t internl node during red; Mke current rtio etween M nd M 3 out 3 to 4 Wnt to design device sizes such tht red current is high enough to crete desired differentil voltge on it lines ~00mV within specified mount of time Cit M 5 I M 6 M 3 (=0) (=) M M M 4 I Cit Cit V = τ, τ trigger Rule-of-Thum: W /W 3 = CMOS SRAM design - write Need to mke sure M 4 is strong enough to pull internl node low while M 6 is trying to pull it high Use switching threshold s trigger point for regenertive switch point; usully wnt to mke it less thn the switching threshold This will force inverter M 5 -M switch to new stte Mke rtio of currents etween M 4 nd M 6 out 3 to 4 M 5 M 3 M 6 ( = 0) (=) M 4 M M ~Gnd 6 Rule-of-Thum: W 4 /W 6 = -.5 3

4 SRAM Cell Lyout Lyout of SRAM word line running horizontlly it lines running verticlly cross-coupled inverters on top ccess trnsistors on ottom Portion of the core rry using SRAM scled in dimensions compred to single it s cross, 3 s high replicted in this mnner to uild the core rry 7 Wordline Cpcitnce Word line presents lrge cpcitnce to the decoder Ech lods the word line with two trnsistor cpcitnces nd one wire cpcitnce (plus wire resistnce) Totl cpcitnce is the cpcitnce per x numer of s on word line clock w Row Address Bits decoder x x x w w3 w4 wordline w5 8 4

5 Column I/O Opertion Circuits tht perform red nd write on the rry re column I/O lod Cn e sttic or prechrged Proper configurtion depends on mplifier design For red Bit lines must strt t round Swings should e smll for fst opertion Involves Mux nd sense mplifier design For write Need to drive one of the itlines to Gnd Mux nd write driver design Often use different I/O lines for red nd write 9 Cpcitnce Lod cpcitnce is mostly self-loding of the s Drin cp nd drin contcts (0.5- ff) of trnsistors re shred Junctions re ised t (lower cp thn norml) Wire cpcitnce ~.ff/micron of wire Row Address Bits clock decoder w w w3 w4 w5 wordline wordline 0 5

6 Lod Options Importnt to equlize itline voltge efore reds, Ltch-sed Ltch-sed Anlog differentil Sense mplifier Sense mplifier Sense mplifier V DD, v V DD V DD V DD -V TN Write Circuitry Prechrge itlines high Pull one column line low Turn on word line Wit until internl vlues of re estlished Turn off word line Design prechrge WL trnsistors to pull it lines high Design write drivers to pull one side low depending on dt vlue pre W D Cit col.sel. M 7 M 8 W D M 3 M 4 M 5 Cit Write Driver clk pre ddr dt col, 6

7 Red Circuitry Prechrge itlines high Turn on word line One line will sloy dischrge Wit until it line reches required low voltge level Turn on column select Amplify difference with sense mplifier pre WL Design sense mplifier sed on desired response time nd power col.enle requirements Use prechrge sed on type of sense mp used. Sense enle Cit M 7 M 8 M 9 M 0 Sense Amplifier Cit Output clk pre ddr dt, col/sense enle out trigger 3 Column Decoder/Mux Need decoder for column ddress followed y mux to select column for input or output opertions Require two outputs to drive complementry pss gtes Since the requirements for red nd write re different cn use seprte red nd write IO lines Hve PMOS ccess for the red IO lines, since the red hppens ner Hve NMOS devices for the write IO lines, since you need to drive itlines to Gnd (see next slide) col ddr C O L U M N D E C O D E R 3 M 4 7

8 Column Muxing Seprte I/O Write Driver Sense Amp Write Driver Sense Amp 5 Multi-Level Column Decoding Alterntives for column selection re tree decoder, regulr decoder + pss trnsistor, or some comintion of the two Shown on the right is tree decoder switches driven directly y ddress its nd their complements totl of M+ devices lrge devices to reduce resistnce long pths -> lrge C -> SLOW To speed up, dd uffers or use djust sizing of devices A A A A COLUMNS B i B i + B i + B i + 3 TREE DECODER SENSE CIRCUIT 6 8

9 Other Options for Column Decoder/Mux Decoders COLUMNS to 4 to 4 7 Building Amplifiers We need n mplifier to hndle smll voltge swings on the it lines for fst opertion Normlly you need to choose etween Drwing DC power (diff. sense mplifier) Using clock edge (ltch-sed mplifier) (to turn DC power on only when the signl is present) For CMOS logic gtes When input is t VDD or Gnd, one of the trnsistors is off Nothing cn hppen until this trnsistor turns on And even then you need to wit some more for gte to switch Sitting in low gin region of trnsfer curve For n mplifier Wnt to e in high-gin region (sturtion) 8 9

10 Ltch-sed Sense Amplifier It must sense very smll signl It must consume smll re Need one for ech itline Or sets of itline (4 or 8) Simplest design: Two ck-to-ck inverters Add clocked pulldown Once Bit nd Bit_ re estlished, turn on pulldown device to ctivte inverters Side with lower voltge will drop to 0V while the other side stys high Bit SenseEnle VDD Bit_ 9 Using Clocks nd Regenertion Three stges of opertion Prechrge Smple Regenerte At the end of smple Smll itline voltge on sense nd sense_ Regenerte M nd M3 turn on Voltge difference cuses current difference Which cuses lrger voltge difference Sense_ M SenseEnle M M3 Sense 0 0