Embedded RISC Microcontroller Core Peripheral

Transcription

1 Features 28-bit Prescaler Programmable Time-out Period Fully Synchronous Protected Turn-off Sequence Up to 100% Fault Coverage with Scan Test Description The AVR embedded RISC microcontroller core is a low-power, CMOS 8-bit microprocessor based on the AVR RISC architecture. With this core, Atmel supplies a. The generates a timeout signal if it has not been reset after a certain number of clock cycles. This can be used to exit from endless loops. The is a fully synchronous peripheral. Figure 1. Pin Configuration cp2 ireset runmod dbus_in[7:0] cs cs_adr[5:0] adr[5:0] iore iowe Timer dbus_out[7:0] out_en Embedded RISC Microcontroller Core Peripheral wdri wdtmout wdcnt[28:0] Scan Test test_se test_si test_so Scan Test Rev. 1344A 02/00 1

2 Table 1. Pin Description Pin Name Function I/O Comments cp2 CPU Clock Input Any register in the watchdog will update its content only on the rising edge of cp2. ireset Synchronous Reset Input When high, ireset will reset internal registers by reading the value on dbus_in which is forced to zero by the AVR core. runmod Run Control Input When low, runmod stops all the internal functions (count) of the watchdog. Only the interface register continues to function normally. dbus_out[7:0] Data Bus Output Output Valid only when accompanied by a strobe on out_en, otherwise held at zero. dbus_in[7:0] Data Bus Input Input Data bus input. out_en Output Enable Output When high, out_en indicates that the watchdog is requiring the control of the data bus. cs Chip Select Input When adr[5:0] = cs_adr[5:0] and cs is high, the is addressed and iore and iowe are active. cs_adr[5:0] Chip Select Address Input base address. When cs is high and adr[5:0] = cs_adr[5:0], the is addressed and iore and iowe are active. cs_adr is NOT dynamic and therefore MUST be established at power-up. adr[5:0] I/O Address Input Valid only when accompanied by a strobe on iore or iowe iore I/O Read Strobe Input Used to read the content of the I/O location addressed by adr. iowe I/O Write Strobe Input Used to update the content of the I/O location addressed by adr. wdri Reset Input Input reset instruction input. When high, wdri resets the watchdog. wdtmout Time-out Output Depending on WDTCR[3:0], wdtmout will indicate the time-out of the watchdog. wdcnt[28:0] Counter Output State of internal watchdog timer. Test Scan test_se Scan Enable Output Input Test scan enable (active high). test_si Scan Chain 1 Input Input Scan chain input. test_so Scan Chain 1 Output Output Scan chain output. Figure 2. cp2 wdri From Control Register WDTCR WDP0 WDP1 WDP2 WDP3 WDE f CP2 /16K f CP2 /32K f CP2 /64K f CP2 /128K f CP2 /256K f CP2 /512K f CP2 /1024K f CP2 /2048K f CP2 /4096K f CP2 /8192K f CP2 /16384K f CP2 /32768K f CP2 /65536K f CP2 /131072K f CP2 /262144K wdtmout 2

3 Functional Description The is clocked by the system clock cp2. By controlling the watchdog timer prescaler, the watchdog timeout interval can be adjusted from 16K to 262,144K x T CP2. The WDR - Reset - instruction resets the watchdog timer. Fifteen different multiples of the clock cycle period can be selected to determine the timeout period. If the timeout period expires without another watchdog reset, the wdtmout pin is held high during half the watchdog timeout period, or until wdri is asserted. This assertion must reset the AVR core. To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled. Refer to the description of the Control Register for details. Chip Select (CS) The watchdog timer has the ability to be remapped inside the AVR I/O address range. To access the internal I/O location of the watchdog timer, the following conditions must be true: adr[5:0] = cs_adr[5:0] cs = 1 Under these conditions, iore and iowe are used to access internal I/Os to read or to write. The cs_adr bus input is NOT dynamic and therefore must be set at power-up. Instead of cs_adr, cs may be used dynamically to decode, for example, multiple I/O pages. The binary value of cs_adr[5:0] is the Base Address (BaseAdr) for addressing. It locates the Control Register WDTCR. THE WATCHDOG TIMER CONTROL REGISTER - WDTCR Bit BaseAdr - - WDTTOE WDE WDP3 WDP2 WDP1 WDP0 WDTCR Read/Write R R R/W R/W R/W R/W R/W R/W Initial value Bits Res : Reserved bits: These bits are reserved bits and will always read as zero. Bit 5 - WDTOE : Turn-off Enable: This bit must be set (one) when the WDE bit is cleared. Otherwise, the will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for the watchdog disable procedure. Bit 4 - WDE : Enable: When the WDE is set (one) the is enabled, and if the WDE is cleared (zero) the watchdog timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is already set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical zero to WDE. This disables the watchdog. Bits WDP3, WDP2, WDP1, WDP0 : Prescaler 3, 2, 1 and 0: The WDP3, WDP2, WDP1 and WDP0 bits determine the prescaling when the is enabled. The different prescaling values and their corresponding timeout periods are shown in Table 2. The WDP3, WDP2, WDP1 and WDP0 bits must be set before enabling the. 3

4 Table 2. Prescale Select WDP3 WDP2 WDP1 WDP0 Timeout Period K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP K x T CP Reserved Scan Test Configuration The AVR peripheral has been designed with a full scan methodology which results in a 100% maximum fault coverage. The coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order to acheive this, the ATPG vectors must be generated on the entire circuit (top level) which includes the AVR. The scan test pins can then be connected for serial or parallel scan. 4

5 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA TEL (408) FAX (408) Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) FAX (44) Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) FAX (852) Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan TEL (81) FAX (81) Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO TEL (719) FAX (719) Atmel Rousset Zone Industrielle Rousset Cedex France TEL (33) FAX (33) Fax-on-Demand North America: 1-(800) International: 1-(408) Web Site BBS 1-(408) Atmel Corporation Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditions located on the Company s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel s products are not authorized for use as critical components in life support devices or systems. Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1344A 02/00/xM