Lecture 11 Digital Circuits (I) THE INVERTER

Transcription

1 Lecture 11 Digital Circuits (I) THE INVERTER Outline Introduction to digital circuits The inverter NMOS inverter with resistor pull-up Reading Assignment: Howe and Sodini; Chapter 5, Sections Spring 27 Lecture 11 1

2 1. Introduction to digital circuits: the inverter In digital circuits, digitally-encoded information is represented by means of two distinct voltage ranges: V V MAX V OL logic 1 undefined region logic V MIN The Static Definition Logic : V MIN V V OL Logic 1: V V MAX Undefined logic value: V OL V Logic operations are performed using logic gates. Simplest logic operation of all: inversion inverter 6.12 Spring 27 Lecture 11 2

3 Ideal inverter IN OUT IN OUT=IN 1 1 Circuit representation and ideal transfer function: v+ V+ = + + V V V+ M = 2 V+ Define switching point or logic threshold : V M input voltage for which = For < V M = V + For V M < V + = Ideal inverter returns well defined logical outputs ( or V + ) even in the presence of considerable noise in (from voltage spikes, crosstalk, etc.) signal is regenerated! 6.12 Spring 27 Lecture 11 3

4 Real inverter logic 1 V MAX slope=-1 transition region logic V OL V MIN V + In a real inverter, valid logic levels defined as follows: Logic : V MIN output voltage for which = V + V OL smallest output voltage where slope = -1 Logic 1: largest output voltage where slope = -1 V MAX output voltage for which = 6.12 Spring 27 Lecture 11 4

5 Two other important voltages: logic 1 V MAX undefined region slope=-1 logic V OL V MIN range of input values that produce valid logic 1 V IL V IH range of input values that produce valid logic V + Define: V IL smallest input voltage where slope = -1 V IH highest input voltage where slope = -1 If range of output values V OL to is wider than the range of input values V IL to V IH, then the inverter exhibits some noise immunity. ( Voltage gain > 1) Quantify this through noise margins Spring 27 Lecture 11 5

6 Chain of two inverters: M noise N VIN NM H V IH VOL NM L V IL inverter M output inverter N input Define noise margins: NM H -V IH NM L V IL -V OL noise margin high noise margin low 6.12 Spring 27 Lecture 11 6

7 Simplifications for hand calculations: Logic levels and noise margins It is hard to compute points in transfer function with slope = -1. Approximate in the following way: =V MAX slope= A v = V M V OL =V MIN V IL V M V IH V + Assume V OL V MIN and V MAX Trace tangent of transfer function at V M Slope = small signal voltage gain (A v ) at V M V IL intersection of tangent with = V MAX V IH intersection of tangent with = V MIN 6.12 Spring 27 Lecture 11 7

8 Transient Characteristics Inverter switching in the time domain: 9% 5% 1% V OL t t R t F t PHL t PLH 9% 5% 1% V OL t t t F R t CYCLE t R t F t PHL t PLH rise time between 1% and 9% of total swing fall time between 9% and 1% of total swing propagation delay from high-to-low between 5% points propagation delay from low-to-high between 5% points Propagation delay : t P = 1 ( 2 t PHL + t PLH ) 6.12 Spring 27 Lecture 11 8

9 Simplifications for hand calculations: Propagation delay Consider input waveform is an ideal square wave Propagation delay times = delay times to 5% point t CYCLE V OL t t PHL t PLH VOH V OL 5% t CYCLE t SPICE essential for accurate delay analysis 6.12 Spring 27 Lecture 11 9

10 2. NMOS inverter with pull-up resistor V + =V DD R I R I D C L load capacitance (from following stages) Essential features: V BS = (typically not shown) C L summarizes capacitive loading of the following stages (other logic gates, interconnect lines, etc.) Basic Operation: If < V T, MOSFET is OFF = V DD If > V T, MOSFET is ON small Value set by resistor / nmos divider 6.12 Spring 27 Lecture 11 1

11 V DD + R I R V R - VOUT I D Transfer function obtained by solving: I R = I D Can solve graphically: I V characteristics of load: 6.12 Spring 27 Lecture 11 11

12 Overlap I V characteristics of resistor pull-up on I V characteristics of transistor: I R =I D load line V DD V GS =V DD R V GS = V GS =V T V DD V DS = Transfer function: =V DS V DD V DD V T =V GS 6.12 Spring 27 Lecture 11 12

13 Logic levels: =V DS V MAX =V DD = V M V MIN V T V M V DD =V GS For V MAX, transistor is cut-off, I D = : V MAX = V DD For V MIN, transistor is in linear regime; solve: I D = W L µ nc ox V DD V MIN 2 V T V MIN = I R = V DD V MIN R For V M, transistor is in saturation; solve: I D = W 2L µ n C ox( V M V T) 2 = I R = V DD V M R 6.12 Spring 27 Lecture 11 13

14 Noise Margins: =V DS V MAX =V DD A v = V MIN V DD V T =V GS Small signal equivalent circuit model at V M (transistor in saturation): R G + + v in v gs gm v gs D r o + v out - - S v in gm v in (r o //R) v out - - A v = v out v in = g m ( r o //R) g m R 6.12 Spring 27 Lecture 11 14

15 What did we learn today? Summary of Key Concepts Logic circuits must exhibit immunity to noise in the input signal Noise margins Logic circuits must be regenerative Able to restore clean logic values even if input is noisy. Propagation delay: time for logic gate to perform its function. Concept of load line: graphical technique to visualize transfer characteristics of inverter. First-order solution (by hand) of inverter figures-ofmerit easy if regions of operation of transistor are correctly identified. For more accurate solutions, use SPICE (or other CAD tool) Spring 27 Lecture 11 15