VIETNAM NATIONAL UNIVERSITY HOCHIMINH CITY THE INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRICAL ENGINEERING

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1 VIETNAM NATIONAL UNIVERSITY HOCHIMINH CITY THE INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRICAL ENGINEERING DESIGN OF A DIGITAL BASE FPGA LOCK-IN AMPLIFIER By Nguyen Nhat An Advisor Udo Klein, PhD A thesis submitted to the School of Electrical Engineering in partial fulfillment of the requirements for the degree of Bachelor of Electrical Engineering. Ho Chi Minh City, Vietnam 2012

2 CHAPTER I: INTRODUCTION 1.1. Problems statement: I want to use a lock-in amplifier to measure a very small signal in the presence of noise, where the noise signal is stronger than the signal I want to measure. For example, a typical opamp can have an equivalent input noise density of 2.5 nv/sqrt(hz). If I use this opamp in a circuit with a bandwidth of 20 khz, the input noise of the opamp is sqrt(20 khz)*2.5 nv/sqrt(hz) = 354 nv. That means I will not be able to detect signal amplitudes that are not much bigger than 354 nv. If my signal is not much bigger than 354 nv, I need to reduce the bandwidth in order to differentiate the signal from the noise. For example, if my signal has a frequency of 100 Hz, I can use a bandpass filter with a centre frequency of 100 Hz and a bandwidth of 1 Hz. The noise voltage is now sqrt(1 Hz)*2.5 nv/sqrt(hz) = 2.5 nv. I can now detect signal amplitudes as low as 2.5 nv. The problem is: _ It is nearly impossible to make a high-q bandpass filter with exactly the right centre frequency. _ Any small changes in the signal frequency will lead to a mismatch between signal frequency and bandpass centre frequency. A better way of reducing the bandwidth is a lock-in amplifier. In that case, I mix the signal frequency with itself, resulting in a frequency component at dc and at twice the signal frequency. Even if the signal frequency changes slightly, the mixing product will still be at dc. To reduce the bandwidth, I can now use a narrow low-pass filter. As a result, I don't have to worry about the exact centre frequency or a change of the signal frequency. If I choose a low- 1

3 pass filter with an upper cutoff frequency of 1 Hz, I have reduced the noise voltage again to 2.5 nv and any signal amplitude above 2.5 nv can be detected. Figure 1: Effect of Low Pass Filter [1] The above diagram shows the distribution of noise and signal power from the optical detector in terms of power per unit bandwidth as a function of frequency. It is important to note that the y axis in this diagram is in units of power per unit bandwidth so the total noise and signal powers are represented by the area under the corresponding curves. Clearly therefor we can immediately improve the signal to noise ratio in this system by using an electronic filter to reject the higher frequency components which do not contain any signal information. However, tradictional analog LIAs are costly because of the required precision and quality of the analog components. It is therefore advantageous to build a digital LIA using signal processing software and standard digital components. The goal of this project is to evaluate the performence of a digital LIA based on Altera Cyclone FPGA technology and experiment on an 2

4 Infrared board. The FPGA LIA provides a low-cost, flexible solution that can be easily reconfigured and adapted to any particular application. [1] All digital FPGA based LIA, page Project objectives: There are some objectives need to be accomplished throughout this thesis: - To build all digital LIA on a FPGA board (Altera Cyclone DE II). - To design the digital components using Verilog HDL and interconnect the modules by building a system, using the SOPC (System On Programmable Chip) builder on Quartus II software. - To program for the microprocessor Nios II (which is built by SOPC builder) using Nios II IDE software. - To design the VGA interface using C programming language and embedded it on the Nios II processor using Nios II IDE software - To desgin a simple transceiver circuit to do experiment and see the sensibility of this LIA. 3

5 CHAPTER II: BACKGROUND 2.1. About lock-in amplifier algorithm How a lock-in work: Mathematically, we can derive the lock-in algorithm as follows. Consider the case where a noise-free sinusoidal signal voltage Vin is being detected, where: Vin = Acos(ωt) ω is the angular frequency of the signal, which is related to the frequency, f, in hertz by the equality: ω = 2 πf The LIA is supplied with a reference signal at frequency f derived from the same source as the signal and uses this to generate an internal reference signal of Vref = B cos(ωt + θ) where θ is a user-adjustable phase shift introduced within the LIA. The detection process consists of multiplying these two components so that the output voltage is given by: V out = A cos (ωt). B cos (ωt + θ) = AB cosωt (cos ωt cos θ - sin ωt sin θ) = AB(cos2ωt cos θ - cos ωt sin ωt sin θ) = AB((½ + ½cos 2ωt)cos θ - ½sin 2ωt sin θ) = ½AB((1+ cos 2ωt)cos θ - sin 2ωt sin θ) 4

6 = ½AB(cos θ + cos 2ωt cos θ - sin 2ωt sin θ) = ½ABcos θ + ½AB(cos 2ωt cos θ - sin 2ωt sin θ) = ½ABcos θ + ½ABcos(2ωt + θ) The output are one AC signal and one DC signal, one at the difference frequency and the other at the sum frequency. If the output is passed through a low pass filter in order to remove the AC signal. However, if two phase are equal, the difference frequency component will be a DC signal. In this case, the filtered output will be: V out = ABcos θ proportional to the magnitude of the input signal A. proportional to the cosine of the angle, θ, between it and the reference signal. The output from the product then passes to a low-pass filter, which removes the 2ωt component, leaving the output of the LIA as the required DC signal. Initially, the signal is multiplied by a reference signal in a frequency mixer and the result is filtered using a low pass filter. In order to function correctly, reference signal must be supplied either externally or the reference signal must be extracted from the measurement signal. The figure 2.a below show the multiplication of two signal in the same phase. Demodulator output has double frequency and DC level reach the maximum value while the figure 2.b is the multiplication between two quadrature signal. The result of this is also a signal which has double phase but is offset equal 0 (minimum value). 5

7 Figure 2.a: Signal and reference in-phase. Figure 2.b: Signal and reference quadrature. [1] [1] 2009-Wiley-Handbook of Measuring System Design, page

8 Structure of a Lock-in amplifier: Figure 3: Simplified Lock-in block diagram. [1] Figure 3 shows a block diagram of a basic implementation of a LIA. A LIA is intended for precise measurement of AC signals. The noise is removed on the input signal at the frequency and phase carried by the reference signal. The LIA acts as a narrow band-pass filter around the reference signal frequency. The reference signal is generated inside Nios II processor. Frequency, magnitude and phase of a pure sine and cosine wave are already known. That sine wave is then mixed with the amplified signal (amplification is optional). For each frequency component in the input signal, 7

9 the mixer generates two output components: one with the frequency equal to the difference between the frequencies of the internal reference and the signal component (ω R - ω S ) and one equal to the sum of the two frequencies (ω R + ω S ). For the component of the input signal with the frequency equal to that of the internal reference (ω S =ω R ), the first mixer component will have frequency equal to 0 (a DC signal) and the second mixer component will have frequency equal to twice the reference frequency (2ω R ). A low-pass filter that follows the mixer should ideally reject everything but the DC component, which is proportional to the amplitude of the signal component at the ω R and the cosine of its phase relative to the phase of the internal reference (A cos(θ) ). This quantity is referred to as X. If the same process, mixing and filtering, is applied using a pure cosine wave at ω R, quantity Y will be generated. Y is proportional to the amplitude of the signal component times the sine of the phase shift (A sin(θ)). From these two quantities, the amplitude (A) and relative phase (R) of the input signal can be determined. In practice, however, the low-pass filter will reject only frequencies that are outside of its cutoff frequency range. Consequently, all noise in the range (ω R filter cut-off frequency) will pass through the filter and adversely affect the measurement. That is why the characteristics of the output filter are of crucial importance to making fast and precise measurements. When speaking about lock-in amplifiers, filter bandwidth is expressed in seconds (timeconstant or TC) instead of in frequency. This is because TC is directly proportional to the filter settling time. If we define the cutoff frequency as the frequency at which the signal is attenuated 3 db (multiplied by the filter order for higher order filters), the IIR filter lock-in engine has a cutoff frequency equal to 1/(2π TC) Hz. The TC is the filter time constant expressed in seconds. [1] NILockinStartupKit, page 4. 8

10 2.2. Analog lock-in amplifier: Figure 4: The functional block diagram of general analog LIA. [1] The block diagram of a conventional analog lock-in amplifier is shown in Figure 4 The system consists of an input amplifier stage that amplifies the signal to a suitable level for further manipulation, perhaps performing an impedance conversion in the process. A band-pass filter is then used to remove any signal components that are either at the DC level or at harmonics of the signal to be measured. The next stage is the Phase Sensitive Detector, also known as a synchronous demodulator or mixer. This circuit can take many forms, from a logarithmic 9

11 amplifier to dedicated four-quadrant multipliers. The input signal is multiplied by a reference signal derived from the system being measured. Since the reference signal must maintain a fixedphase relationship to the input signal, it is often locked to the reference signal using a Phase- Locked Loop (PLL). A further refinement commonly found on commercial devices is the dual channel function. In this case the input is mixed with the reference, and is also mixed with a 90 degree phase-shifted version of the reference. This channel function has the useful property that it is then quite simple to directly calculate the magnitude of the input and its phase relationship to the reference. These two separate channels are normally called the In-Phase component and the Quadrature component, or I and Q, respectively. Finally, the output from the mixers is fed into low-pass filters, which effectively remove any non-coherent signals, leaving a final DC signal proportional to the amplitude and phase of the input signal. There are a number of problems with analog lock-in amplifiers: _ For the highest accuracy, the reference signal must have a very low harmonic content. In other words, it must be a very pure sine wave since any additional harmonic content will cause distortion at the output. _ Analog sine wave generators can also suffer from amplitude variations due to temperature drift. _ Temperature drift and component tolerances elsewhere in the system can cause further problems in the analog system. _ Real world op amps have offsets associated with them that need careful trimming to prevent errors in the DC output. _ Finally, any non-linearity in gain and phase will lead to further errors in the final output. 10

12 While these problems are not insurmountable, the result is that analog lock-in amplifiers tend to be expensive pieces of equipment and are more often used if high-input bandwidths are required Digital Lock-in amplifier: Figure 5: General digital LIA. [2] In the case of a digital lock-in amplifier, most of the processing is performed in the digital domain using software and dedicated Digital Signal Processing (DSP) hardware. The basic block diagram for a digital lock-in amplifier is shown in Figure 5. The system still features a front-end amplifier; however, this is then followed by an anti-aliasing filter to remove any 11

13 signal components higher than half the sampling frequency. For an audio core on DE2, the sampling would be performed from 14-bit to 32-bit. In practice, the filter may have a much narrower band than this, and for a signal of interest at 1.5 khz, the filter may be set as low as 4 Hz. The reference signal is generated internally or can be derived from sampling an external signal. In the case of internally generated signals, the individual sample points of the reference signal can be calculated to a high degree of accuracy, and therefore do not suffer from the typical errors found in the analog Lock-In. The reference signal is also phase-shifted by 90 degrees by either a table lookup or simple mathematical operations. Next, the reference and phase-shifted reference values are multiplied directly by the DSP to generate the intermediate I and Q signals. Finally, these signals are passed through digital low-pass filters to generate the final output values. Interestingly, it is the digital low-pass filter stage that can cause the most implementation problems for the software engineer. The data being sampled is arriving at a high rate, and even though the output filters could be operating at only a few Hertz. The amount of RAM required for the implementation can become prohibitively large and result in a costly implementation. However, as is shown later, some clever DSP techniques can be used which reduce these requirements. Once the input signal has been quantized by the analog-to-digital converter, there is no further loss of signal quality. Furthermore, since the reference signal can be digitally computed, it can be made to have a very low harmonic content. Most importantly, the deviations due to non-linear gain and phase of the analog components are removed in the digital lock-in amplifier and there will be no variations due to temperature drift or component aging. Similarly, the offsets associated with real analog components are removed and the limitation on intermediate accuracy is purely down to the resolution of the processor and DSP engine. [1] DSP Lock-In Amplifier model RS830, page 32. [2] Implementing digital lock-in amplifiers using the dspic DSC. 12

14 CHAPTER III: DESIGN A DIGITAL FPGA LOCK-IN AMPLIFIER 3.1. Hardware implementation High Level Design: The main technical objective of this research is to build all digital cost efficient lock-in amplifiers using FPGA board which could be used to perform the measurements as requires on the next part of the project. It would be designed individually as modules. The lock-in designed here follows the general picture described below, with a few practical compilations. A high level schematic of the LIA can be seen in figure 6: Figure 6: High level schematic of lock-in amplifier 13

15 The reference signal would be generated by a fixed set frequency onboard direct digital synthesis unit. Once mixed down, the signal are fed through programmable digital filter and are then measure and routed by a Nios II processor. The signal output can be directly routed to analog output ports as well as displayed. For simplicity, both design and conceptual, the low pass filter were implemented via a single pole IIR filter configured to emulate an analog RC filter. This design allowed implementation using minimal system resources as well as minimal complexity, while also allowing easy calculation of filter parameters when changing settings. The parameter could be generated by the Nios from a user selected time constant. The single pole filter was implemented with two multipliers with filter output given by: Out = a0 * in + b1 * out_previous. Time constant was selected by turning a0 and b1 according to: b1 = e^(-1/d) a0 = 1 a0 where d is the time required to decay to 1/e in number of clock ticks. In order to allow maximal flexibility of the device, Nios II processor was also implemented to control the signal path. Although not explicitly shown in figure, the Nios acts as a high level control system, switching signals from the lockin components to the output. In this fashion, the output DACs can be used to output signal form any part of the signal path including the reference sources, giving the advantage of maximal flexibility as well as a useful tool in debugging. In addition, the Nios can be used to control filter operation/decay time.. 14

16 Implementing these components in FPGA allows all operations after A/D sampling to be done digitally at high speed. The target platform for this project was the Altera DE2 board with a Cyclone II FPGA, speed grade 6, with 35k logic elements. The lockin design should fit easily within this chip and looking up the speed specs for this speed grade gives an advertised 18 x 18 bit multiplication of over 200MHz. This type of clock speed is probably not attainable for the system a whole, but clocking at 50MHz should be entirely stable. As a reasonable expectation, input signal sine waves operating at frequency 1.5KHz should be easily achievable at these clock rates. User interface: For basic lockin functionality, a number of settings must be entered and displayed by the user. Control of the reference, whether external or an internally set frequency, as well filter badwidth are essential. In addition control of the output signals along with the ability to display information about current measured values is useful. To this end, it was decided to generate a VGA output from Nios II processor. The Nios II processor provided plenty of processing power to generate an output display as well as handle user input and control elements of the lockin signal path. This design was made for the Altera Cyclone II DE2 board from Terasic. The snapshot of the board is shown in figure 7. 15

17 Figure 7: Altera Cyclone II DE2 FPGA board The major advantage of DE2 board was it supports the hardware components needed, such as the the basic FPGA support circuitry (power supply, programming, ect), as well switches and buttons for user input along with VGA output port. For the purpose of the design, the input signal is first fed into the A/D of Audio port which is then multiplied in a multiplier and passed though the low pass filter. The audio port also use for performance reference sine wave which is generated by program. The signals are processed by NIOS II processor include multiplier, digital low pass filter, reference generator and doing communications with other peripheral such as: LCD, VGA, switches, buttons, LED 16

18 Verilog HDL design: The entirety of the digital components of this project were implemented on a Terasic DE2 board with an Altera Cyclone II FPGA. The DE2 board provided the majority of the hardware components needed, such as the basic FPGA support circuity (power supply, programming ) as well switches and buttons for user input along with a VGA output port. The important port on this board for a lockin is a high speed audio A/D converters. The Audio Core supports both, audio input and audio output simultaneously. Figure 8 shows a block diagram of the Audio Core. To guarantee that the left and right audio output channels are synchronized, data will not play until both channels are received. If only one channel is to be played, the other channel must have zeros written to it. The Audio Core contains four FIFOs for the In and Out audio data, both having the right and left audio channels. Each FIFO can store up to bit words. The Audio Core requires certain clock frequencies based on the sample rate of the audio. It also requires that the audio chip be initialized with some default values. These requirements are met by using some other University Program IP cores, which are described below. 17

19 Figure 8: Block diagram for Audio Core The DE2 Media Computer has three types of memory components: SDRAM, SRAM, and on-chip memory inside the FPGA chip. Each type of memory is described below: An SDRAM Controller provides a 32-bit interface to the synchronous dynamic RAM (SDRAM) chip on the DE2 board, which is organized as 1M x 16 bits x 4 banks. It is accessible by the Nios II processor using word (32-bit), halfword (16- bit), or byte operations, and is mapped to the address space 0x to 0x007FFFFF. An SRAM Controller provides a 32-bit interface to the static RAM (SRAM) chip on the DE2 board. This SRAM chip is organized as 256K x 16 bits, but is accessible by the Nios II processor using word (32-bit), halfword (16-bit), 18

20 or byte operations. The SRAM memory is mapped to the address space 0x to 0x0807FFFF. The red lights LEDR17 0 and green lights LEDG8 0 on the DE2 board are each driven by an output parallel port, as illustrated in Figure 9. The port connected to LEDR contains an 18-bit write-only Data register, which has the address 0x The port for LEDG has a nine-bit Data register that is mapped to address 0x These two registers can be written using word accesses, and the upper bits not used in the registers are ignored. Figure 9: Output parallel ports for LEDR and LEDG The top-level Verilog file call DE2_media_computer.v which defines ports that correspond to all of the user-acessible pins on the Cyclone II FPGA. 19

21 Figure 10: Verilog HDL top-level file Nios II design Using the SOPC builder of Quartus II software a system had to be built on the chip that would interconnect all the verilog modules as physical components on the FPGA board driven by the NIOS II processor clocked at 50 MHz. The purposes of this part are: 20

22 Using the SOPC Builder to design a Nios II-based system Integrating the designed Nios II system into a Quartus II project Implementing the designed system on the DE-series board Ready for running lock-in program on the Nios II processor Figure 11: A Nios II system implemented on a DE2 board Altera s Nios II is a soft processor, defined in a hardware description language, which can be implemented in Altera s FPGA devices by using the Quartus II CAD system. To implement a useful system it is necessary to add other functional units such as memories, input/output interfaces, timers, and communications interfaces. To facilitate the implementation 21

23 of such systems, it is useful to have computer-aided-design (CAD) software for implementing a system-on-a-programmable-chip (SOPC). Altera s SOPC Builder is the software needed for this task. For a fuller treatment of the SOPC Builder, the reader can consult the Nios II Hardware Development Tutorial. A complete description of the SOPC Builder can be found in the Quartus II Handbook Volume 4: SOPC Builder. These documents are available on the Altera web site. An example Nios II system can be implemented on a DE-series board as shown in Figure 11. Altera s SOPC Builder software, which is used to implement a system that uses the Nios II processor on an Altera FPGA device. The last step in the development process involves configuring the designed circuit in an actual FPGA device, and running an application program. The SOPC design is shown in fig.12, which was compiled without any errors. Figure 12: SOPC design using SOPC builder 22

24 Figure 13: Verilog top file Nios II system module The instantiation of the generated module depends on the design entry method chosen for the overall Quartus II project. I have chosen to use Verilog HDL, but the approach is similar for both VHDL and schematic entry methods. All we need to do is instantiate the Nios II system in our top-level Verilog file, and connect inputs and outputs of the parallel I/O ports, as well as the clock and reset inputs, to the appropriate pins on the Cyclone-series device. The Verilog module generated by the SOPC Builder is in the file nios_system.v in the directory of the project. Note that the name of the Verilog module is the same as the system name specified when first using the SOPC Builder. The Verilog code is quite large. Figure 13 depicts the portion of the code that defines the input and output signals for the module nios_system. The clock and reset signals are 23

25 called clk_0 and reset_n, respectively. Note that the reset signal is added automatically by the SOPC Builder, it is called reset_n because it is active low. After successful compilation of SOPC builder the files that were required to program the DE2 board were obtained. It was then programmed using the Quartus II programmer. All the verilog modules were successfully programmed into the board. Figure 14: Quartus II compilation report After building successful hardware using Quartus II and SOPC builder, I continue to load the.sof file which include all hardware design information on DE2 board: 24

26 Figure 15: Loading sof file into DE2 board Now, the NIOS II had to be programmed to embed the c user interface. Using the NIOS II IDE the c file lockin.c which described in the next part (software development) was compiled. The ptf file obtained by the SOPC builder was used to detect the CPU used for the system. The file could be compiled successfully without any errors. I also used LCD, The DE2 Media Computer includes a liquid crystal display (LCD) port that is connected to the 16x2 character display on the DE2 board. The display includes a memory for storing character data. This LCD shows some parameter of this lock-in such as: cutoff frequency, order of low pass filter. The main result would be show through VGA port. The DE2 Media Computer includes a video-out port with a VGA controller that can be connected to a standard VGA monitor. The VGA controller supports a screen resolution of 640 x 480. The image that is displayed by the VGA controller is derived from two sources: a pixel buffer, and a character buffer. That would be the big advantages for using Nios to do the interface. 25

27 3.2. Software development In this part, I would show modules which are written by C using Nios IDE software Interrupt with audio core: The Audio Core produces a read interrupt when either of the read FIFOs are filled to 75% or more. The interrupt is cleared when the FIFO becomes less than 75% full. Also, it produces a write interrupt when either of the write FIFOs have available space of 75% or more. The interrupt is cleared when the FIFO becomes less than 75% empty. The Audio Core generates an interrupt when either of these individual interrupt conditions are pending and enabled. Flow chart for Audio core interrupt: 26

28 Figure 16: Audio core interrupt flowchart. 27

29 3.2.2 Button interrupt: Figure 17: Registers used for interrupts from the pushbutton parallel port. Figure 12 shows the registers associated with the pushbutton parallel port. The Interruptmask register allows processor interrupts to be generated when a key is pressed. Each bit in the Edgecapture register is set to 1 by the parallel port when the corresponding key is pressed. The Nios II processor can read this register to determine which key has been pressed, in addition to receiving an interrupt request if the corresponding bit in the interrupt mask register is set to 1. Writing any value to the Edgecapture register deasserts the Nios II interrupt request and sets all bits of the Edgecapture register to zero. So, from these register, I developed flow chart and C code for this part. The purposes for using these button are: start/stop program, emit reference signal and play_back signal after processing. 28

30 Figure 18: Button interrupt flow chart Main program: The low pass filter in main program was design from book Introduction to signal processing. Parameters were calculated and replay in the transfer function of a simple low pass filter. 29

31 The table of creating sine and cosine signal would be taking from page 49 of book Digital Signal Processing and application with C6713. After developed all the function for lock-in such as signal generator, multiplier, low pass filter, result computations. The final step for this design would be connect those function and run it on Nios. Figure 19: main program flowchart of lock-in amplifier 30

32 The program was primarily to implement the user interface as well as control the filters and operating mode of the lockin. The interface consisted of a text display with various changeable settings as well as continually updated outputs of the lockin. By reading in the measured values of the two quadratures of the lockin, the NIOS could both display these values on screen, as well as calculate derivative quantities. Useful information that was chosen for display was the total response of the lockin(r) as well as the measured phase angle. These value were easily calculated: R^2 = X^2 +Y^2 Theta = Atan(X/Y) Where X and Y are the measured values of the two quadratures. In all likelihood, this was entirely unnecessary as the only speed requirement be that the output values update at a reasonable human timescale for display. 31

33 4.1. Experiment: CHAPTER IV: EXPERIMENT AND RESULTS The small signal I want to detect is the signal resulting from the reflection of IR light. The noise signal is caused by general electrical noise and by other light detected by the phototransistor, other than the reflected IR light. Because there is a lot of light in the environment, the reflected IR light is expected to be small compared to the total noise signal at the phototransistor's output. If I want to distinguish the weak reflected IR signal from the noise, I need to create a narrow-band signal frequency by modulating the IR LED with a known reference frequency, in your case the 1.5 khz of the oscillator. I then use the lock-in amplifier to mix the photo-transistor output signal with the reference signal. As a result, the reflected IR signal component that is modulated with the reference frequency of 1.5 khz is now mixed down to DC. After low-pass filtering the down-converted signal, you have the reflected IR signal together with all noise signals that were in the same bandwidth around the reference frequency as the cutoff frequency of the low-pass filter. Since the noise is usually distributed over a large bandwidth, but the signal of interest is concentrated at the reference frequency of 1.5 khz, I can expect that the signal of interest is larger than the noise signal. Of course, there are still limits on how small the signal of interest can be and how much noise can allow. Anyway, I now have the signal of interest, the narrow-band reflected IR signal, separated from the wide-band noise at the output of the photo-transistor. But what I am really interested in is any information in this signal of interest, that means any change of the signal of interest (= change of reflected IR light). 32

34 I therefore build an experiment, where I change the reflected IR signal and look at the change of the signal of interest as a result of the change of reflected IR light. I can do that, by shining the IR light on changing surfaces that reflect more or less of the IR light, depending on the colour of the surface. The changes that I can detect do of course have limitations. Changes of the signal of interest will generate frequency components around the reference frequency of my signal. For example, if the changes have a frequency of 10 Hz, I will have frequency components at 1.5 khz +/- 10 Hz. After mixing this signal with the reference frequency, I will have the interesting part of the signal at 10 Hz. That means, the cutoff frequency of the low-pass filter needs to be above 10 Hz in order to be able to detect the changes in the signal of interest. So I have two contradictory requirements for the cutoff frequency of the low-pass filter: As low as possible in order to reduce noise But high enough to be able to detect the highest frequency change in the signal of interest Figure 20: Schematic for an experiment transceiver circuit 33

35 All of the experiment would be shown in the Thesis defense presentation Results In this part I would show the results from testing every module in the lockin. Because of the limitation of time and the size of this project. I refer to take more time to make the lockin run on experience and perform in the Thesis defense presentation. Reference generator: Figure 21: Sine and cosine reference signal 34

36 The Altera DE2 generating sine and cosine with 1v magnitude and 1.5 khz frequency. This signal would be used to drive the Infrared board in the experiment. Low pass filter Figure 22: Testing low pass filter 35

37 The low pass filter was tested using software Multi-Instrument Pro 3.2 and my laptop audio port. The reference signal has 500 frequency(red line) was generated by above software and emitted from audio line-out in my laptop. This signal would be pass through audio line-in on DE2 board and filtered by a simple first order low pass filter program in Nios. The result(blue line) is the signal go from audio line-out on DE2 board to audio line-in in my laptop and performed on screen using software Multi-Instrument. CHAPTER V: CONCLUTIONS AND FUTURE DEVELOPS 1. Conclusions: In general, analyzing rough costs asscociated with this form of lockin device yields tantalizing results. The current design when compiled nad fitted into the Cyclone II FPGA used around logic elements. Given that this includes a full feature 32 bit processor with instruction cache, as well as number of other entirely non-space-optimized components, it seems reasonable that the entire design could be fit within device. In conclusion, the lockin devoce described here was a cuccess, if somewhat limited by the hardware used. Building upon the basic device with better, customized hardware could yield a device suitable for high quality measurements.despite the need for better engineering of analog components here, the mostly digital design would still seem to be simpler to engineer than an all analog device and offers tantalizing possibilities. 36

38 2. Future developments: Base on results which I achieved in this project. I will make it better such as: o o o Improve the gain and performance of design. Design all modules, and function using Verilog language. Increase the sensibility of design 37

39 REFERENCES [1] Audio_core, Vailable: [2] DE2 user manual, Available: b7 [3] DE2_media_computer, Available: [4] Nios II Software Developer s handbook, Available: [5] All Digital FPGA Based LIA Available: [6] Lock-in amplifier project, Available: [7] IIR filter design, Available: [8] Design of IIR filter. Available: [9] Handbook of operational amplifier applications, Bruce Carter and Thomas R.Brown, Texas Instruments application report Available: [10] sine_table from book Digital Signal Processing and Applications with the C6713 And C6416 Dsk (Rulph Chassaing), page

40 [11] Low pass filter design parameters: Intro.To.Signal.Processing. Orfanidis, page: 569, Available: k_e_y= &ich_t_y_p_e=1&ich_d_i_s_k_i_d=1&ich_u_n_i_t=1 [12] Design on an FPGA, Available: [13] SDRAM_ControllerWithAvalon, Available: 39

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