MM74C164 8-Bit Parallel-Out Serial Shift Register

Transcription

1 8-Bit Parallel-Out Serial Shift Register General Description The MM74C164 shift registers are a monolithic complementary MOS (CMOS) integrated circuit cotructed with N- and P-channel enhancement traistors. These 8-bit shift registers have gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. A high-level input enables the other input which will then determine the state of the flip-flop. Data is serially shifted in and out of the 8-bit register during the positive going traition of clock pulse. Clear is independent of the clock and accomplished by a low level at the clear input. All inputs are protected agait electrostatic effects. Features October 1987 Revised January 2004 Supply voltage range: 3 to 15 Tenth power TTL compatible: drive 2 LPTTL loads High noise immunity: 0.45 CC (typ.) Low power: 50 nw (typ.) Medium speed operation: 0.8 MHz (typ.) with 10 supply Applicatio Data terminals Itrumentation Medical electronics Alarm systems Industrial electronics Remote metering Computers MM74C164 8-Bit Parallel-Out Serial Shift Register Ordering Code: Order Number Package Number Package Description MM74C164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74C164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table Serial Inputs A and B Inputs Output t n t n+1 A B Q A Top iew 2004 Fairchild Semiconductor Corporation DS

2 Block Diagram 2

3 Absolute Maximum Ratings(Note 1) oltage at Any Pin 0.3 to CC Operating Temperature Range 55 C to +125 C Storage Temperature Range 65 C to +150 C Absolute Maximum CC 18 Power Dissipation (P D ) Dual-In-Line 700 mw Small Outline 500 mw Operating CC Range 3 to 15 Lead Temperature (soldering, 10 seconds) 260 C Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditio for actual device operation. MM74C164 DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditio Min Typ Max Units CMOS TO CMOS IN(1) Logical 1 Input oltage CC = CC = IN(0) Logical 0 Input oltage CC = CC = OUT(1) Logical 1 Output oltage CC = 5, I O = 10 µa 4.5 CC = 10, I O = 10 µa 9.0 OUT(0) Logical 0 Output oltage CC = 5, I O = +10 µa 0.5 CC = 10, I O = +10 µa 1.0 I IN(1) Logical 1 Input Current CC = 15, IN = µa I IN(0) Logical 0 Input Current CC = 15, IN = µa I CC Supply Current CC = µa CMOS TO LPTTL INTERFACE IN(1) Logical 1 Input oltage CC = 4.75 CC 1.5 IN(0) Logical 0 Input oltage CC = OUT(1) Logical 1 Output oltage CC = 4.75, I O = 360 µa 2.4 OUT(0) Logical 0 Output oltage CC = 4.75, I O = 360 µa 0.4 OUTPUT DRIE (See Family Characteristics Data Sheet) (Short Circuit Current) I SOURCE Output Source Current CC = 5, IN(0) = 0 T A = 25 C, OUT = ma I SOURCE Output Source Current CC = 10, IN(0) = 0 T A = 25 C, OUT = ma I SINK Output Sink Current CC = 5, IN(1) = 5 T A = 25 C, OUT = CC 1.75 ma I SINK Output Sink Current CC = 10, IN(1) = 10 T A = 25 C, OUT = CC 8.0 ma 3

4 AC Electrical Characteristics (Note 2) T A = 25 C, C L = 50 pf, unless otherwise noted Symbol Parameter Conditio Min Typ Max Units t pd1 Propagation Delay Time to a Logical 0 or a CC = Logical 1 from Clock to Q CC = t pd0 Propagation Delay Time to a Logical 0 from CC = Clear to Q CC = t S Time Prior to Clock Pulse that Data CC = Must be Present CC = t H Time After Clock Pulse that CC = Data Must be Held CC = f MAX Maximum Clock Frequency CC = CC = MHz t W Minimum Clear Pulse Width CC = CC = t r, t f Maximum Clock Rise and Fall Time CC = 5 15 CC = 10 5 µs C IN Input Capacitance Any Input (Note 3) 5 pf C PD Power Dissipation Capacitance (Note 4) 140 pf Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C PD determines the no load AC power coumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90. Typical Applicatio 74C Compatibility Guaranteed Noise Margin as a Function of CC 4

5 Logic Waveform MM74C164 AC Test Circuit Switching Time Waveforms CMOS to CMOS TTL to CMOS t r = t f =

6 Physical Dimeio inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 6

7 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) MM74C164 8-Bit Parallel-Out Serial Shift Register 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness