Philips PNX7850E/Z DVD Multimedia Processor Process Review

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Silas Ross Collins
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1 April 5, 2006 Philips PNX7850E/Z DVD Multimedia Processor Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Process Review Table of Contents 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Polysilicon 3.7 Isolation, Resistors and Capacitors 3.8 Wells and Substrate 4.1 Cell Overview 4.2 SRAM Analysis 5 ROM Analysis 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions Report Evaluation

3 Overview List of Figures 2 Device Overview Top Package View Bottom Package View Package X-Ray (Top-View) PNX7850E/Z Die Die Markings Die Markings Die Corner Die Corner Die Corner Die Corner Bond Pads General View of PNX7850E/Z Die Edge Die Seal Structure Bond Pad Bond Pad Edge Passivation IMD IMD IMD IMD PMD I/O Transistors Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal Metal Minimum Pitch Via 3s Minimum Pitch Via 2s Via 1s Via 0s Minimum Pitch Contacts to Diffusion Contacts to Polysilicon Minimum Gate Length NMOS Transistor Minimum Gate Length PMOS Transistor Minimum Pitch Polycide NMOS I/O Transistor Two NMOS I/O Transistors

4 Overview Poly Over Isolation Minimum Width Isolation Resistors (Optical) Resistors (SEM) Capacitor (Optical) Capacitor Bottom Plate Contact (SEM) Capacitor Top Plate Contact (SEM) Logic P-Well SCM N-Well SEM with N-Well Stain in the Analog Region T-SRAM Cell Metal 2 Power Buses and Bit Lines Metal 1 Word Lines Metal 0 Local Interconnects SRAM Gates SRAM at Diffusion SEM Cross-Section of Pull-up Transistors SEM Cross-Section of Access and Pull-down Transistors 5 ROM Analysis ROM Optical View 1.2 List of Tables Device Summary Process Summary Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor and Polycide Dimensions SRAM Transistor Sizes 6 Critical Dimensions Minimum Pitch Metals Contacts and Vias Die, Transistors, Poly and Isolation Vertical Dimensions

5 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

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