Exercise 1: Trigger Levels of TTL and CMOS Gates
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1 TTL and CMOS Comparison Digital Logic Fundamentals Exercise 1: Trigger Levels of TTL and CMOS Gates EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the input voltage at which the output of a TTL gate or a CMOS gate changes logic states by using the TTL/CMOS COMPARISON circuit block. You will verify your results with an oscilloscope and a multimeter. EXERCISE DISCUSSION TTL gates use a positive supply voltage of 5 Vdc. The negative supply voltage is ground. CMOS gates use a positive supply voltage (V DD ) of 5, 10, or 15 Vdc. The negative supply voltage (V SS ) is less than the input and output voltages, and the input and output voltages are less than V DD. 270 FACET by Lab-Volt
2 Digital Logic Fundamentals TTL and CMOS Comparison The positive supply voltage and negative supply voltage for a CMOS gate are a. V CC and ground, respectively. b. V DD and V SS, respectively. TTL and CMOS gates will not change output states when the input voltage is less than the input low voltage (V IL IH At some input voltage between V IL and V IH, the gate output state changes; this input voltage is the trigger level. When the input to a TTL or CMOS gate is greater than V IH, the input is in a(n) a. logic 0 state. b. uncertain logic state. c. logic 1 state. TTL maximum V IL = 0.8 Vdc minimum V IH = 2.0 Vdc FACET by Lab-Volt 271
3 TTL and CMOS Comparison Digital Logic Fundamentals The table shows the TTL buffer (7407) output logic state that corresponds to an input voltage. For the TTL gate, an input voltage between 0 Vdc and 0.8 Vdc is considered low, and the output is low. Between 0.8 Vdc and 2.0 Vdc, the logic state of the input is uncertain, and consequently the output logic state is uncertain. 272 FACET by Lab-Volt
4 Digital Logic Fundamentals TTL and CMOS Comparison At an input voltage of 2.0 Vdc and above, the input is high and the output is high. Actually, the output changes state at an input voltage (trigger level) in the uncertain region between 0.8 and 2.0 Vdc. When a 7407 TTL buffer has an input voltage of 0.7 Vdc, the input is in a(n) a. logic 0 state. b. uncertain state. c. logic 1 state. FACET by Lab-Volt 273
5 TTL and CMOS Comparison Digital Logic Fundamentals CMOS The CMOS gate output changes state at an input voltage between a V IL and a V IH that depend on the supply voltage (V DD ). For a 4069UB CMOS gate with V DD at 5.0 Vdc, V IL is 1.0 Vdc and V IH is 4.0 Vdc. For a 4069UB CMOS gate with V DD at 10.0 Vdc, V IL is 2.0 Vdc and V IH is 8.0 Vdc. 274 FACET by Lab-Volt
6 Digital Logic Fundamentals TTL and CMOS Comparison For a 4069UB CMOS gate with V DD at 15.0 Vdc, V IL is 2.5 Vdc and V IH is 12.5 Vdc. The output changes state at an input voltage (trigger level) in the uncertain region between V IL and V IH. When the input voltage for a 4069UB CMOS gate with V DD at 15 Vdc is 10 Vdc, the input is in a(n) a. logic 0 state. b. uncertain logic state. c. logic 1 state. Noise Margins In general, CMOS gates have better noise margins than TTL gates do. The difference between V IH and V IL is an indication of the noise immunity of a gate: V noise = V IH V IL. FACET by Lab-Volt 275
7 TTL and CMOS Comparison Digital Logic Fundamentals A CMOS gate used on the circuit board has a V IH of 4.0 Vdc and a V IL of 1.0 Vdc at a V DD of 5.0 Vdc. The highest noise, the extra signal superimposed on the authentic logic level, that the input could receive without changing state is calculated as follows: V noise = = 3.0 Vdc. For the TTL gate, V noise is only 1.2 Vdc ( ). Power Consumption is practically no input current. Consequently, the power consumed and heat dissipated are very low compared to a TTL gate, which is a current device. However, at very high clock frequencies (switching rates), the power consumption of a CMOS gate increases to TTL consumption levels. Which gates have a high noise immunity and lower power consumption? a. TTL b. CMOS 276 FACET by Lab-Volt
8 Digital Logic Fundamentals TTL and CMOS Comparison A 7407 buffer is an open-collector gate. It can convert TTL levels into CMOS levels. Standard TTL gates cannot operate above V CC ; however, the open-collector output can be pulled to V DD. The CMOS (4069UB) gate does not require pull-up resistors, but they are added to the circuit to provide a sharp contrast between the gate supply voltages (V DD and V SS ). DD at 5 Vdc, or CMOS with V DD at S, the supply voltage (V CC or V DD ), for gate and resistor pull-ups. FACET by Lab-Volt 277
9 TTL and CMOS Comparison Digital Logic Fundamentals PROCEDURE TTL Gate Locate the TTL/CMOS COMPARISON circuit block. Connect a test lead between the positive variable supply and the TTL gate input, as shown. This is the schematic of the TTL buffer circuit. 278 FACET by Lab-Volt
10 Digital Logic Fundamentals TTL and CMOS Comparison Connect the positive voltmeter lead to the input (V I ) of the TTL gate, and connect the negative ground lead to a ground terminal on the circuit board. Adjust the positive variable supply for a TTL gate input voltage (V I ) less than 0.4 Vdc. Connect the oscilloscope channel 1 probe to the TTL gate output (V O ), and connect the probe ground clip to a ground terminal on the circuit board. On channel 1 of the oscilloscope, measure the TTL gate output low voltage (V OL ). Your answer should be in mv. V OL = mvdc (Recall Value 1) FACET by Lab-Volt 279
11 TTL and CMOS Comparison Digital Logic Fundamentals With V S (V CC = 5 V) connected to the TTL gate output by a pull-up resistor, what no load output high voltage (V OH ) would you expect? V OH = Vdc (Recall Value 2) The maximum low-level input voltage (V IL means that the gate output will not switch from a low to a high until the input voltage is above 0.8 Vdc; the gate recognizes inputs below V IL as low. The minimum high-level input voltage (V IH that the gate output will switch from a low to a high before the input voltage is above 2.0 Vdc; the gate recognizes inputs above V IH as high. In other words, at an input voltage between 0.8 Vdc and 2.0 Vdc, the TTL gate output changes logic states. While observing V O on channel 1 of the oscilloscope, adjust the positive variable supply to slowly increase V I until V O switches from a low (0 Vdc) to a high (5 Vdc). At what input voltage did the output switch from low to high? V I = Vdc (Recall Value 3) Is the measured value of the input voltage ( Vdc [Step 9, Recall Value 3]) when the output switched to high greater than V IL (0.8 Vdc) and less than V IH (2.0 Vdc)? a. yes b. no 280 FACET by Lab-Volt
12 Digital Logic Fundamentals TTL and CMOS Comparison What is the output voltage of the TTL gate indicated on channel 1 of the oscilloscope screen? V O = Vdc (Recall Value 4) Adjust the input voltage to 5.0 Vdc. While observing V O on channel 1 of the oscilloscope, adjust the positive variable supply to slowly decrease V I until V O switches from a high (5 Vdc) to a low (0 Vdc). At what voltage did the output switch from high to low? V I = Vdc (Recall Value 5) Is the measured value of the input voltage ( Vdc [Step 12, Recall Value 5]) when the output switched to low less than V IH (2.0 Vdc) and greater than V IL (0.8 Vdc)? a. yes b. no FACET by Lab-Volt 281
13 TTL and CMOS Comparison Digital Logic Fundamentals CMOS Gate A CMOS gate can operate with the V DD (V S ) supply voltage at 5, 10, or 15 Vdc. However, the DD (V S ) only at 5 or 15 Vdc. Set S1 to CMOS. Keep S2 set to +5 V to select a V DD (V S ) of 5 V. Maintain the multimeter and oscilloscope connections. The maximum low-level input voltage (V IL means that the gate output will not switch from a low to a high until the input voltage is above 1.0 Vdc; the gate recognizes inputs below V IL as low. The minimum high-level input voltage (V IH means that the gate output will switch from a low to a high before the input voltage is above 4.0 Vdc; the gate recognizes inputs above V IH as high. In other words, at an input voltage between 1.0 Vdc and 4.0 Vdc, the CMOS gate output changes logic states. 282 FACET by Lab-Volt
14 Digital Logic Fundamentals TTL and CMOS Comparison Set the input voltage (V I ) to the CMOS gate to less than 0.4 Vdc by adjusting the positive variable supply. While observing V O on channel 1 of the oscilloscope, adjust the positive variable supply to slowly increase V I until V O switches from a low (0 Vdc) to a high (5 Vdc). At what input voltage does the output switch from low to high? V I = Vdc (Recall Value 6) Is the measured value of the input voltage ( Vdc [Step 19, Recall Value 6]) when the output switched to high greater than V IL (1.0 Vdc) and less than V IH (4.0 Vdc)? a. yes b. no What is the output voltage of the CMOS gate indicated on channel 1 of the oscilloscope screen? V O = Vdc (Recall Value 7) FACET by Lab-Volt 283
15 TTL and CMOS Comparison Digital Logic Fundamentals Adjust the input voltage to 5.0 Vdc. While observing V O on channel 1 of the oscilloscope, adjust the positive variable supply to slowly decrease V I until V O switches from a high (5 Vdc) to a low (0 Vdc). At what input voltage did the output switch from high to low? V I = Vdc (Recall Value 8) Is the measured value of the input voltage ( Vdc [Step 22, Recall Value 8]) when the output switched to low less than V IH (4.0 Vdc) and greater than V IL (1.0 Vdc)? a. yes b. no Interfacing a TTL Open Collector Gate with a CMOS Gate Connect the circuit shown. Set S1 to CMOS and set S2 to +15 V. 284 FACET by Lab-Volt
16 Digital Logic Fundamentals TTL and CMOS Comparison The schematic for the connected circuit is shown. The open collector TTL buffer (7407) is connected to a 15 Vdc pull-up resistor and to the input of the CMOS buffer (two 4069UB) with V DD equal to 15 Vdc. Connect the voltmeter to the input of the TTL gate, and connect the oscilloscope channel 1 probe to the output of the CMOS gate. FACET by Lab-Volt 285
17 TTL and CMOS Comparison Digital Logic Fundamentals Set the positive variable supply to 0 Vdc. Slowly increase the positive supply voltage until the output of the CMOS gate changes state. At what input voltage to the TTL buffer did the CMOS gate change state? V I = Vdc (Recall Value 9) With the oscilloscope, measure the output voltage of the TTL buffer as shown in the image below. What is the TTL output voltage? V O = Vdc (Recall Value 10) What is the output voltage of the logic 1 state of the CMOS gate? V O = Vdc (Recall Value 11) 286 FACET by Lab-Volt
18 Digital Logic Fundamentals TTL and CMOS Comparison CONCLUSION The positive power supply for TTL gates is designated V CC and is set at 5 Vdc; the negative power supply is ground. The positive power supply for CMOS gates is designated V DD and is set at 5, 10, or 15 Vdc; the negative power supply is designated V SS, which is less than the input or output voltages. CMOS gates have a wider range between the input low voltage (V IL ) and input high voltage (V IH ). An open collector TTL gate can drive a CMOS gate when the TTL open collector output has a pull-up resistor connected to V DD. CMOS gates have better noise immunity and lower power consumption than TTL gates. REVIEW QUESTIONS 1. The positive power supply level (V CC ) of a TTL gate is nominally a. 15 Vdc. b. 10 Vdc. c. 5 Vdc. d. None of the above. 2. The positive power supply level (V DD ) of a CMOS gate is nominally a. 15 Vdc. b. 10 Vdc. c. 5 Vdc. d. Any of the above. 3. The voltage difference between the V IL and V IH a. the same as a CMOS gate. b. greater than a CMOS gate. c. less than a CMOS gate. d. dependent on V CC. 4. When a TTL gate drives a CMOS gate, the a. CMOS gate must be an open collector with V DD equal to V CC. b. TTL gate must be an open collector with V CC equal to V DD. c. TTL gate must be an open collector with the output pulled up to V DD. d. TTL gate and the CMOS gate must have equal supply voltages. 5. CMOS gates have better noise immunity than TTL gates because a. the voltage difference between V IL and V IH is greater for CMOS gates. b. the voltage difference between V IL and V IH is less for CMOS gates. c. V DD is usually greater than V CC. d. TTL gates have open collector outputs. FACET by Lab-Volt 287
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