Microcontroller multi-core Architecture: A real world device solving real world problems.

Transcription

1 Microcontroller multi-core Architecture: A real world device solving real world problems. NXP Microcontrollers ARM User Conference Birmingham, UK 16 May, 2012

2 NXP is a leader in ARM Flash MCUs Clear strategy: 100% focus on ARM Top performance through leading technology & architecture 8051 ARM9 ARM7 Design flexibility through pin- and software-compatible solutions Scalable memory sizes Widest range of peripherals Unlimited choice through complete families for multiple cores Cortex M0 Cortex M3 Cortex M4

3 NXP Changing Microcontroller Landscape Breaking through traditional boundaries of 8b, 16b, 32b and DSP cost performance 8-bit 16-bit 32-bit DSP Very low-end 8b e.g. 6-8 pin not planned ARM Cortex-M Continuum Cortex-M0 Cortex-M3 Cortex-M4 High-end DSP/MPU not planned Binary and tool compatible The ONLY vendor that offers the full range of ARM Cortex-M microcontroller families

4 Cortex-M Processors: Binary Compatible

5 Rapidly growing family of Cortex-M microcontrollers For more information: Cortex-M4 Up to 204MHz LPC4300 LPC40xx High performance M4/M0 DSC with advanced peripherals High-performance M4 with USB, Ethernet, LCD, and more Cortex-M3 Up to 180MHz LPC1800 LPC1700 LPC1300 Memory options up to 1MB flash, 200k SRAM High-performance with USB, Ethernet, LCD, and more USB solution, incl. on-chip USB drivers Cortex-M0 Up to 50MHz LPC1200 LPC1100 Memory options up to 128k flash Best-in-class dynamic power consumption 5 COMPANY CONFIDENTIAL 5

6 LPC4300 Dual-Core MCU Introduction to NXP and Cortex-M4 based LPC4300 More than one processor why? Symmetric Asymentric Asymmetric topologies Bus infrastructure Resources Communication Hardware Software Asymmetric Applications Debugging 6

7 NXP Microcontrollers Cortex-M4, LPC4300 NXP Cortex-M4, introducing multicore processing to microcontroller and DSP applications Cortex-M4 based Digital Signal Controller featuring a highly flexible Cortex-M0 subsystem Unique configurable peripherals especially suitable for motor control, solar inverter, digital power and audio applications Cortex-M4 Cortex-M0 + = LPC4300 Processing Application Audio/Image Processing Control Algorithm Real Time Control + Peripheral Control = Solution! Protocol Emulation Digital Multicore award for NXP LPC4000 dual core microcontroller design

8 Introducing the LPC4300 Family LPC4300 Cortex-M4 based Digital Signal Controller Cortex-M0 peripheral sub-system with dedicated configurable smart I/O and event handling Up to 1 MB Flash Dual-Bank Flash provides safe inapplication programming (IAP) Large SRAM: up to 264 KB SRAM SPI Flash Interface with four lanes and up to 40MB/s data transfer rate. State Configurable Timer Subsystem Serial GPIO (SGPIO) Two High-speed USB 2.0 interfaces. An on-chip High-speed PHY 10/100 Ethernet MAC LCD panel controller (up to 1024H 768V) Two 10-bit ADCs and 10-bit DAC at 400ksps Eight-channel General-Purpose DMA (GPDMA) controller Motor Control PWM Quadrature Encoder Interface 4x UARTs, 2x I2C, 2x I2S, CAN 2.0B, 3x SSP/SPI Smart card interface Up to 146 general purpose I/O pins LPC1800 Cortex-M3 LPC4300 Cortex-M4 Pin/Peripheral Compatible

9 LPC4300 Part Numbers Part# Flash Total Flash A Flash B SRAM LCD Ethnt HS USB Max Freq Package LPC KB 0 KB 0 KB 264 KB Y Y BGA256, BGA180, LQFP208 LPC KB 0 KB 0 KB 264 KB Y BGA256, BGA180, BGA100, LQFP144 LPC KB 0 KB 0 KB 200 KB BGA100, LQFP144 LPC KB 0 KB 0 KB 168 KB 204 BGA100, LQFP144 Part# Flash Total Flash A Flash B SRAM LCD Ethnt HS USB Max Freq Package LPC MB 512 KB 512 KB 136 KB Y Y BGA256, BGA180, LQFP208 LPC KB 256 KB 256 KB 136 KB Y Y BGA256, BGA180, LQFP208 LPC MB 512 KB 512 KB 136 KB Y BGA256, BGA180, BGA100, LQFP144 LPC KB 256 KB 256 KB 136 KB Y BGA256, BGA180, BGA100, LQFP144 LPC MB 512 KB 512 KB 136 KB BGA100, LQFP144 LPC KB 384 KB 384 KB 136 KB BGA100, LQFP144 LPC KB 256 KB 256 KB 104 KB BGA100, LQFP144 LPC KB 512 KB 0 KB 104 KB BGA100, LQFP144 LPC MB 512 KB 512 KB 136 KB 204 BGA100, LQFP144 LPC KB 384 KB 384 KB 136 KB 204 BGA100, LQFP144 LPC KB 256 KB 256 KB 104 KB 204 BGA100, LQFP144 LPC KB 512 KB 0 KB 104KB 204 BGA100, LQFP144 9

10 Asymmetrical Dual Core

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12 Symmetric processing Improved processing performance by distributing work load across N processors of the same type Complex Cache Coherency Requires OS support Amdahl's law ( can t get 1/N speed up) Communication limitations as the number of cores increase Hardware Software Core 1 Cache Core 2 Cache Program Memory 12

13 Asymmetric processing Not intended to distribute 1 task over multiple cores Intended to process different applications Separate program resource per core Specialized OS not required Simple hardware for processor communication Core 1 Program Memory Core 2 Program Memory 13

14 M series microcontroller cores Thumb 2 Hardware Divide 1.25 DMIPS/MHz Thumb 2 DSP support 1.25 DMIPS/MHz Cortex M4 Thumb Only No hardware divide 0.9 DMIPS/MHz Cortex M3 Cortex M0 14

15 Asymmetric Implementation Cortex M4 with DSP extensions Including FPU for computation Cortex M0 for control and communication Cortex M4 Cortex M0 Program Memory Program Memory 15

16 Simple IPC (inter-processor communication) TXEV CREG Interrupt NVIC Write Pointer SRAM HOST_CMD_BUFFER Read Pointer Cortex M4 AHB Cortex M0 Read Pointer SRAM HOST_MSG_BUFFER Write Pointer NVIC Interrupt CREG TXEV 16

17 LPC4300 Bus Matrix JTAG interface Debug Port LCD interface Ethernet PHY interface USB ULPI interface USB FS SDIO interface X32kin X32kout Xtalin Xtalout RST FPU TEST/DEBUG INTERFACE ARM Cortex-M4 or M3 EMULATION TRACE MODULE ARM Cortex M0 DMA M0 subsystem controller 2x LCD controller Ethernet 10/100 MAC USB2.0 HS OTG/ Host/ Device USB2.0 HS Host/ Device SDIO controller Clock Generation, Power Control, and other System Functions VBAT VDD VDDA VSSA VSS I-bus D-bus S-bus adapter adapter Clocks and Controls ROM 64kB SRAM 72kB Bus Master Bus Slave Memory Adapter SRAM 128kB SRAM 32kB ETM SRAM 32kB c4 AHB Matrix AHB slaves adapter c1 c2 c3 External Memory controller adapter APB slaves1 adapter APB slaves2 adapter APB slaves3 adapter APB slaves4 SPIFI HS GPIO 12b ADC AES State Cfg Timer adapter APB slaves5 AHB master regs 17

18 LPC4300 Flash Banks Two 512K byte banks of flash memory. Can be used as a single 1M byte memory area. Enhanced memory controller and 256-bit wide interface allows operation at up to 204MHz. Flash B Flash A Contiguous Mode Flash B Flash A Dual Mode 18

19 LPC4300 Memory Model M4 and M0 can execute from FLASH without contention M0 can execute from its own RAM (4 options) ROM written in thumb mode means both M4 and M0 can use ROM code M4 MPU can be used to protect M0 code space. 19

20 Cortex-M0 Subsystem: Bus Matrix Connections LPC4300 CORTEX-M4 204MHz S I D CORTEX -M0 204MHz Maximum performance is obtained when the code for each processor is located in different memories. Cortex-M DMIPS/MHz Cortex-M0 0.9 DMIPS/MHz ROM SRAM 128 KB AHB Matrix 72 KB 32 KB 16 KB + 16 KB External Memory Ctrl Both Cortex-M4 & Cortex-M0 can run at 204 MHz

21 LPC4300 Boot sequence M0 Reset ROM Boot Code M4 Starts up first M0 IPC Loaded FLASH A FLASH M0 prep Asd code Optional RAM execution M0 code Execution from flash B M4 code execution from flash A Application Code 21

22 Cortex-M0 Subsystem: Audio Processing LPC4300 Cortex-M4: Full power devoted to Audio processing Cortex-M0: Handles the hardware control I 2 S & USB I 2 S Cortex-M4 Cortex-M0 LPC4300 USB

23 Cortex-M0 Subsystem: Audio Processing LPC4300 HS PHY FS PHY + ULPI CORTEX-M4 204MHz CORTEX -M0 204MHz GPDMA Ether net USB0 USB1 SD/ MMC LCD S I D 0 1 ROM SRAM 128 KB AHB Matrix 72 KB 32 KB 16 KB + 16 KB External Memory Ctrl AHB Peripherals APB Peripherals

24 Cortex-M0 Subsystem: Motor Control LPC4300 Cortex-M4: Single shunt Field Oriented Control (FOC) Cortex-M0: Receives control commands via CAN interface Cortex-M4 Cortex-M0 SCT CAN Command LPC4300

25 Cortex-M0 Subsystem: Motor Control LPC4300 HS PHY FS PHY + ULPI CORTEX-M4 204MHz CORTEX -M0 204MHz GPDMA Ether net USB0 USB1 SD/ MMC LCD S I D 0 1 ROM SRAM 128 KB AHB Matrix 72 KB 32 KB 16 KB + 16 KB External Memory Ctrl AHB Peripherals APB Peripherals

26 LPC4300 Debug view Both cores are on the same JTAG chain Treated as separate cores Full Trace for M4 26

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