C166S V1 Multiply- Accumulate Unit

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1 , V 1.0, August S V1 Multiply- Accumulate Unit 166S V1 MA Microcontrollers ever stop thinking.

2 dition Published by Infineon Technologies AG, St.-Martin-Strasse 53, D München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies omponents may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

3 , V 1.0, August S V1 Multiply- Accumulate Unit 166S V1 MA Microcontrollers ever stop thinking.

4 166S V1 MA Revision History: V1.0 Previous Version: - - Page Subjects (major changes since last revision) We Listen to Your omments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

5 Table of ontents Page 1 MA Unit Features nhanced Addressing apabilities Multiply-Accumulate Unit Program ontrol MA Unit Instruction Pipelining Address Generation oreg Addressing Mode umber Representation and Rounding MA Unit omponents x 16 Signed/Unsigned Parallel Multiplier oncatenation Unit Sign xtension Unit and Scaler bit Signed Arithmetic Unit bit Signed Accumulator Register Data Limiter Accumulator Shifter Repeat Unit MA Unit Interrupt MA Unit Register Set MA Unit Address Registers Accumulator Registers MA Unit Status Word (MSW) MA Unit ontrol Word (MW) MA Unit Repeat Word (MRW) Syntax List of MA Unit Instructions Instruction Index Keyword Index S V1 MA, User s Manual I-1 V 1.0,

6 166S V1 MA, User s Manual I-2 V 1.0,

7 List of Tables Page Table 1 Pointer Post-modification ombinations for IDXi and Rwn Table 2 Parallel Data Move Addressing Table 3 oreg 5-bit Addressing Mode Table 4 Data Limiter Output Table 5 Summary S V1 MA, User s Manual II-1 V 1.0,

8 166S V1 MA, User s Manual II-2 V 1.0,

9 MA Unit Features 1 MA Unit Features The Multiply-Accumulate (MA) Unit is a specialized co-processor added to the 166S PU core to improve the performance of signal processing algorithms. It includes: a multiply-accumulate unit an address generation unit capable of feeding the MA Unit with 2 operands per cycle a repeat unit to execute a series of multiply-accumulate instructions The architecture of the MA Unit is outlined in )LJXUH. 166S V1 MA, User s Manual -3- V 1.0,

10 MA Unit Features 16-bit Input Operands oncatenation Unit Signed/Unsigned Multiplier 16-bit 32-bit 40-bit Mux Sign xtend 1-bit Scaler AU Shifter 0h 08000h 0h Mux Mux &6&38,QWHUUXSW &RQWUROOHU 05: Repeat Unit A B 40-bit Signed Arithmetic Unit 0&: ontrol Unit )ODJV 0$( 06: 0$+ 0$/ Data Limiter 0$6 )LJXUH 0$&8QLW$UFKLWHFWXUH 166S V1 MA, User s Manual -4- V 1.0,

11 MA Unit Features The MA Unit includes the following features. 1.1 nhanced Addressing apabilities ew addressing modes, including a double indirect addressing mode with pointer post-modification. Parallel Data Move allows one operand move during multiply-accumulate instructions without penalty. ew transfer instructions ostor (for fast access to the MA Unit SFRs) and omov (for fast memory to memory table transfer). 1.2 Multiply-Accumulate Unit xecution of all MA Unit operations within one PU instruction cycle 16 x 16 signed/unsigned parallel multiplier 40-bit signed arithmetic unit with automatic saturation mode 40-bit signed accumulator 8-bit left/right shifter Scaler (one-bit left shifter) Data limiter Full instruction set with multiply and multiply-accumulate, 32-bit signed arithmetic, and compare instructions Three 16-bit status and control registers: MSW - MA Unit Status Word MW - MA Unit ontrol Word MRW - MA Unit Repeat Word 1.3 Program ontrol Repeat Unit to allow some MA Unit co-processor instructions to be repeated up to 8192 times. Repeated instructions may be interrupted. MA Unit interrupt (implemented as lass B hardware trap) on MA Unit condition flags. 166S V1 MA, User s Manual -5- V 1.0,

12 MA Unit 2 MA Unit MA Unit operation is based on the cores instruction pipeline and extended addressing modes. 2.1 Instruction Pipelining All MA Unit instructions use a 4-stage pipeline. During each stage the following tasks are performed: )(7&+ All new instructions are double-word instructions. '(&2'( If required, operand addresses are calculated and the resulting operands are fetched. IDX and GPR pointers are post-modified if necessary. (;(&87( Performs the MA Unit operation. At the cycle end the accumulator and the MA Unit condition flags are updated if required. Modified GPR pointers are written-back during this stage, if required. :5,7(%$& Operand write-back in the case of parallel data move. 1RWH $W OHDVW RQH LQVWUXFWLRQ QRW XVLQJ WKH 0$& 8QLW PXVW H LQVHUWHG HWHHQ WR LQVWUXFWLRQVWKDWUHDGIURPD0$&8QLWUHJLVWHU7KLVLVHFDXVHWKHDFFXPXODWRU DQGWKHVWDWXVRIWKH0$&8QLWDUHPRGLILHGGXULQJWKH([HFXWHVWDJH 7KH &R6725( LQVWUXFWLRQ KDV HHQ DGGHG WR DOOR DFFHVV WR WKH 0$& 8QLW UHJLVWHUVLPPHGLDWHO\DIWHUD0$&8QLWRSHUDWLRQ 2.2 Address Generation MA Unit instructions can use some of the standard 166 addressing modes such as GPR direct or #data4 for immediate shift value. ew addressing modes were added to supply the MA Unit with two new operands per instruction cycle. These allow indirect addressing with DGGUHVVSRLQWHUSRVWPRGLILFDWLRQ. 'RXOH LQGLUHFW DGGUHVVLQJ requires two pointers. Any GPR can be used for one pointer, the other pointer is provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset registers QR0/QR1 and QX0/QX1 are associated with each pointer (GPR or IDX i ). The GPR pointer allows access to the entire memory space, but accesses via IDX i are limited to the internal dual-port RAM, except for the omov instruction. The various combinations of pointer post-modification for each of the two new addressing modes are shown in 7DOH. Symbols >5 >,'; to these addressing modes. 166S V1 MA, User s Manual -6- V 1.0,

13 MA Unit 7DOH 3RLQWHU3RVWPRGLILFDWLRQ&RPLQDWLRQVIRU,';LDQG5 Q 6\PRO 0QHPRQLF $GGUHVV3RLQWHU2SHUDWLRQ [IDX i ] stands for [IDX i ] (IDX i) (IDX i ) (no-op) [IDX i +] [IDX i -] (IDX i ) (IDX i ) +2 (i=0,1) (IDX i ) (IDX i ) -2 (i=0,1) [IDX i + QX j ] (IDX i ) (IDX i ) + (QX j ) (i, j =0,1) [IDX i - QX j ] (IDX i ) (IDX i ) - (QX j ) (i, j =0,1) [Rw n ] stands for [Rw n ] (Rw n ) (Rw n ) (no-op) [Rw n +] [Rw n -] (Rw n ) (Rw n ) +2 (n=0-15) (Rw n ) (Rw n ) -2 (k=0-15) [Rw n +QR j ] (Rw n ) (Rw n ) + (QR j ) (n=0-15;j =0,1) [Rw n - QR j ] (Rw n ) (Rw n ) - (QR j ) (n=0-15; j =0,1) The omam class of instructions is a certain set of instructions that implement a mechanism called 3DUDOOHO 'DWD 0RYH. The omam instructions exclusively use double indirect addressing mode. Parallel Data Move allows the operand pointed to by IDX i to be moved to a new location in parallel with the MA Unit operation. The writeback address for the Parallel Data Move is calculated depending on the postmodification of IDX i. 166S V1 MA, User s Manual -7- V 1.0,

14 MA Unit It is obtained by the operation "reverse" to the pointer post-modification of IDX i, as explained in 7DOH. 7DOH,QVWUXFWLRQ 3DUDOOHO'DWD0RYH$GGUHVVLQJ :ULWHDF$GGUHVVIRU3DUDOOHO'DWD 0RYH omam [IDX i +],... <IDX i -2> omam [IDX i -],... <IDX i +2> omam [IDX i +QX j ],... <IDX i -QX j > omam [IDX i -QX j ],... <IDX i +QX j > The Parallel Data Move shifts a table of operands in parallel with a computation on those operands. Its specific use is for signal processing algorithms like filter computation. An example of Parallel Data Move using the omam instruction is shown in )LJXUH. 16-bit omam [IDX0+], [R2+] n+2 n+2 IDX0 n n-2 X IDX0 n n-2 X X Parallel Data Move n-4 n-4 )LJXUH Before xecution ([DPSOHRI3DUDOOHO'DWD0RYH After xecution 166S V1 MA, User s Manual -8- V 1.0,

15 2.3 oreg Addressing Mode User s Manual MA Unit The MA Unit accumulator and control registers (MAL, MAH, MSW, MW, MRW) can be addressed by the regular instruction set as any other SFR. In addition, they can be addressed by the &R6725( instruction. The ostor instruction utilizes a specific 5- bit addressing mode called &R5HJ which allows the immediate storage of MA Unit registers after an operation. Addresses of MA Unit registers in oreg addressing mode are shown in 7DOH. 7DOH &R5HJLW$GGUHVVLQJ0RGH 5HJLVWHU LW$GGUHVV MSW MA Unit Status Word MAH MA Unit Accumulator High Word MAS limited MA Unit Accumulator High Word MAL MA Unit Accumulator Low MW MA Unit ontrol Word MRW MA Unit Repeat Word MAS is a YLUWXDO register. If MAS is specified as a source operand for ostor, the MAH register is read through the data limiter. MAS cannot be addressed by regular SFR/ SFR addressing. 2.4 umber Representation and Rounding The MA Unit supports the WR VFRPSOHPHQW representation of binary numbers. In this format the sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to one for negative numbers. Unsigned numbers are supported only by multiply/multiply-accumulate instructions which specify whether each operand is signed or unsigned. In two s complement fractional format the -bit operand is represented using the 1.[-1] format (1 signed bit, -1 fractional bits). This format can represent numbers between -1 and [-1] and is supported when the shift mode bit MP of register MW is set. The MA Unit implements two s complement rounding, where one is added to the bit to the right of the rounding point (bit 15 of MAL) before truncation (MAL is cleared). 166S V1 MA, User s Manual -9- V 1.0,

16 MA Unit omponents 3 MA Unit omponents The major components of the MA Unit are shown in )LJXUH. In the following, all of these components are described in detail x 16 Signed/Unsigned Parallel Multiplier The multiplier executes 16 x 16-bit parallel signed/unsigned fractional and integer multiplications. The multiplier has two 16-bit input ports for the two operands and a 32- bit product output port. The result is always presented in a signed fractional or integer format. 3.2 oncatenation Unit The concatenation unit enables the MA Unit to perform 32-bit arithmetic operations in one PU instruction cycle. It concatenates the two 16-bit operands to a 32-bit operand before the 32-bit operation is executed in the 40-bit arithmetic unit. The second required operand is always the current accumulator content. The concatenation unit is also used to pre-load the accumulator with a 32-bit value. 3.3 Sign xtension Unit and Scaler Prior being fed to the 40-bit signed arithmetic unit, the result of the multiplier (or of the concatenation unit) is sign extended to a 40-bit number. This sign extension replicates the sign bit (MSB) of the word 8 times. With unsigned/unsigned instructions, (e.g. omulu, omau) 8 zero bits are extended regardless of the MSB of the word to be extended. The one-bit scaler can shift the sign extended result one bit to the left. Depending on the type of instruction, the scaler is controlled either by the Product Shift Mode Bit MP (bit 10 in MA Unit ontrol Word - MW) or by the instruction itself. For multiply instructions (if the MP bit is set), the product is automatically shifted left by one bit to compensate for the extra sign bit gained in multiplying two signed 2 s complement numbers. The scaler is also active for instructions such as oadd2, osub2, etc., where the 32-bit operand is doubled before being fed to the arithmetic unit. 166S V1 MA, User s Manual -10- V 1.0,

17 bit Signed Arithmetic Unit User s Manual MA Unit omponents The 40-bit signed arithmetic unit allows intermediate overflows in a series of multiply/ accumulate operations. There are two 40-bit input ports, A and B. The A-input port accepts data as h, h (round), or the sign extended and scaled result of the multiplier or of the concatenation unit. The B-input port is the feedback of the accumulator output sent through the 8-bit left/right shifter. The B-input port can also receive h to allow direct transfer from the A-input port to the accumulator. If, during accumulation, a 40-bit overflow of the accumulator occurs, the sticky overflow flag will be set in the MA Unit Status Word (MSW). The result of the addition/subtraction can be rounded or saturated on a 32-bit value automatically after every accumulation. The rounding is performed by adding h to the result and clearing the Accumulator Low Word MAL. Automatic saturation is enabled by setting the saturation bit MS in the MA Unit ontrol Word (MW). When the accumulator is in the saturation mode and a 32-bit overflow occurs, the accumulator is loaded with either the highest positive or the lowest negative value that can be represented with a 32-bit 2 s complement number, depending on the direction of the overflow. Thus the value of the accumulator upon saturation is 00 7fff ffffh (positive) or ff h (negative). Automatic saturation sets the sticky limit flag () in the MA Unit Status Word (MSW). 1RWH,I DXWRPDWLF VDWXUDWLRQ DQG URXQGLQJ LV SHUIRUPHG 0$/ LOO H FOHDUHG RQ WKH VDWXUDWHGYDOXHDQGWKHUHVXOWDIWHUVDWXUDWLQJDQGURXQGLQJSRVLWLYHQXPHUVLOO H IIIK 1RWH,IWKHDFFXPXODWRUFRQWDLQVDYDOXHWKDWFDQQRWHUHSUHVHQWHG\DLWV FRPSOHPHQWQXPHULH06DVSUHYLRXVO\VHWWRWKHQVDWXUDWLRQFDQRQO\H DFKLHYHG \ VHWWLQJ 06 WR DQG RQH 0$& 8QLW LQVWUXFWLRQ H[HFXWLQJ,I WKLV LQVWUXFWLRQ FDXVHV D LW RYHUIOR RU XQGHUIOR WKHQ WKH YDOXH RI WKH DFFXPXODWRUXSRQVDWXUDWLRQLV III IIIIKRUII K 166S V1 MA, User s Manual -11- V 1.0,

18 bit Signed Accumulator Register User s Manual MA Unit omponents Most co-processor operations specify the 40-bit accumulator register as a source and/or destination operand. The accumulator is comprised of three SFR registers: MAL (MA Unit Accumulator Low Word), MAH (MA Unit Accumulator High Word) and MA (AU xtension). While MAH and MAL are 16-bit wide, MA consist of only 8-bits, which are accessed as the least significant byte of the MA Unit Status Word MSW. MA is the most significant byte of the accumulator. When writing to MAH by regular SFR addressing, the value in the accumulator is automatically adjusted to a sign extended 40-bit 2 s complement format. MAL acquires zero value and MA is automatically loaded with zeros in case of a positive number (MAH has 0 in the most significant bit) and with ones in case of a negative number (MAH has 1 in the most significant bit). ote that the values represented by the 32-bit number and the extended 40-bit number are the same and the MA register does not contain significant bits. This is true whenever the highest 9 bits of the signed 40-bit result are identical. During accumulator operations an overflow may occur and the result may not fit into 32- bits. The accumulator then exceeds the 32-bit boundary and changes the contents of MA. onsequently there are significant (non-sign) bits in the top 8 bits of the accumulator. To indicate this extension, extension flag, contained in the most significant byte of the MA Unit Status Word MSW, is set to Data Limiter Saturation arithmetic is also provided to selectively limit overflow when reading the accumulator by means of a &R6725(GHVWLQDWLRQ!0$6instruction. If the contents of the accumulator cannot be represented by 32 bits without overflow, the limiter is enabled and MAS is modified to a limited value. Otherwise MAS is equal to MAH, as shown in 7DOH. 7DOH 'DWD/LPLWHU2XWSXW (LW 1LW /LPLWHU2XWSXW0$6 0 x equal to MAH 1 0 7fffh h 1RWH 7KH0$6YDOXHLVRQO\UHDGDOH\PHDQVRID&R6725(GHVWLQDWLRQ!0$6 LQVWUXFWLRQ,IH[HFXWHGWKHDFFXPXODWRUDQGWKHVWDWXVUHJLVWHUDUHQRWDIIHFWHG 166S V1 MA, User s Manual -12- V 1.0,

19 3.7 Accumulator Shifter User s Manual MA Unit omponents The accumulator shifter is a parallel shifter with 40-bit input and 40-bit output. The source operand of the shifter is an accumulator and possible shifting operations are: no shift (unmodified) up to 8-bit arithmetic left shift up to 8-bit arithmetic right shift ote that left shift operations affect flags,,, and of the MA Unit Status Word MSW. Therefore, if the automatic saturation mechanism is enabled (MS-bit set to 1), the behavior is similar to that of the 40-bit arithmetic unit. 1RWH &HUWDLQ SUHFDXWLRQV DUH UHTXLUHG LQ FDVHV RI D OHIW VKLIW LQ FRQMXQFWLRQ LWK DXWRPDWLFVDWXUDWLRQHQDOHG06LWVHWWR,IWKH06LWLVHLQJVHWGLUHFWO\ HIRUH WKH OHIW VKLIW LQVWUXFWLRQ FRUUHFW VDWXUDWLRQ LV QRW JXDUDQWHHG XQGHU DOO FLUFXPVWDQFHVVLQFHVLJQLILFDQWLWVPD\KDYHHHQVKLIWHGRXWHIRUHVDWXUDWLRQ LVSHUIRUPHG7RDYRLGWKLVVLWXDWLRQVLWFKRQDXWRPDWLFVDWXUDWLRQHDUOLHUVR WKDWWKHOHIWVKLIWLQVWUXFWLRQLVDOUHDG\RSHUDWLQJRQDVDWXUDWHGYDOXH 3.8 Repeat Unit The MA Unit includes a repeat unit which repeats some co-processor instructions up to 2 13 (=8192) times. The repeat count is specified either by an immediate value (up to 31) or by the content of the repeat count (bits 12 to 0) in the MA Unit Repeat Word (MRW). If the repeat count in MRW equals 1, the instruction will be executed 1 times. At each iteration of a repeated instruction the repeat count is tested for zero. If zero, the instruction is terminated, otherwise the repeat count is decremented and the instruction is repeated. During such repeated sequences, the Repeat Flag MR (bit 15 of the MA Unit Repeat Word (MRW)) is set until the last execution of the repeated instruction. The syntax of repeated instructions is shown in the following examples: Repeat #24 times oma[idx0+],[r0+] ; performed 24 times In this example, the instruction is repeated according to a 5-bit immediate value. The repeat count in MRW is automatically loaded with this value minus one. MOV MRW, #00FFh ; load MRW OP ; instruction latency Repeat MRW times omam [IDX1-],[R2+] ; performed 256 times The instruction is repeated according to the repeat count in MRW. ote that, due to the pipeline processing, at least one instruction should be inserted between MRW write and the next repeated instruction. 166S V1 MA, User s Manual -13- V 1.0,

20 MA Unit omponents Repeat sequences may be interrupted. When an interrupt occurs during a repeat sequence, the sequence is stopped and the interrupt routine is executed. The repeat sequence resumes at the end of the interrupt routine. During the interrupt the repeat flag MR remains set, indicating that a repeated instruction has been interrupted and the repeat count holds the number of repetitions (minus 1) that remain to complete the sequence. If the repeat unit is used in the interrupt routine, MRW must be saved by the user and restored before the end of the interrupt routine. 1RWH 7KH05:UHJLVWHUPXVWHXVHGLWKFDXWLRQ([FHSWIRUUHVWRULQJ05:DIWHUDQ LQWHUUXSW WKH 05 LW VKRXOG QRW H VHW \ XVHU 2WKHULVH FRUUHFW LQVWUXFWLRQ SURFHVVLQJFDQQRWHJXDUDQWHHG 166S V1 MA, User s Manual -14- V 1.0,

21 MA Unit Interrupt 4 MA Unit Interrupt The MA Unit can generate an interrupt corresponding to the value of the status flags (arry), (Sticky Overflow), (xtension) or (Sticky Limit) of the MSW register. The MA Unit Interrupt is globally enabled if the MI flag in MW is set. When enabled, the flags,,, or can trigger a MA Unit Interrupt, provided that the corresponding mask flags M, VM, M, and LM in MW are also set. The MIR flag in MSW is set upon the first interrupt condition. This flag must be cleared during interrupt processing. If this flag is set already, a new interrupt condition cannot trigger an interrupt. The MA Unit Interrupt is implemented as a lass B hardware trap (trap number A H, trap priority I). The associated trap flag in the Trap Flag Register TFR is MATRP (bit 6). ote that when a MA Unit interrupt request occurs, this flag must be cleared by the user. The layout of the Trap Flag Register TFR in the 166S V1.1 is as follows: TFR Trap Flag Register SFR(FFA H,D6 H ) Reset value: 0000 H MI STK OF STK UF UD OP MA TRP 0 0 PRT FLT ILL OPA ILL IA ILL BUS rwh rwh rwh r r r r r rwh rwh r r rwh rwh rwh rwh Field Bits Type Description ILLBUS [0] rwh ILLegal xternal BUS Access 0 o illegal external bus access detected 1 An external access has been attempted with no bus defined. ILLIA 1) [1] rwh ILLegal Istruction Access 0 o illegal instruction access detected 1 A branch to an odd address has been attempt. ILLOPA 1) [2] rwh ILLegal word OPerand Access 0 o illegal word operand access event detected 1 Ilegal word operand access event detected PRTFLT 1) [3] rwh PRoTection FauLT 0 o protection fault event detected 1 Protection fault event detected 166S V1 MA, User s Manual -15- V 1.0,

22 MA Unit Interrupt Field Bits Type Description MATRP [6] rwh MA Unit Interrupt 0 o MA Unit interrupt detected 1 MA Unit interrupt detected UDOP 1) [7] rwh UDefined OPode 0 o undefined opcode event detected 1 Undefined opcode event detected STKUF 1) [13] rwh STacK UnderFlow flag 0 o stack underflow event detected 1 Stack underflow event detected STKOF 1) [14] rwh STacK OverFlow flag 0 o stack overflow event detected 1 Stack overflow event detected MI 1) [15] rwh on-maskable Interrupt flag 0 o non-maskable interrupt detected 1 on-maskable interrupt detected 0 [12, 11, 10, 9, 8, 5, 4] r Reserved read as 0 ; writing to these bit positions has no effect. 1) This bit supports bit protection ote: The trap service routine must clear the respective trap flag. Otherwise, a new trap will be requested after exiting the service routine. Setting a trap request flag by software causes the same effects as if it had been set by hardware. As MA Unit status flags are updated (or written by software) during the execute stage of the pipeline, the response time of a MA Unit Interrupt Request is 3 instruction cycles, as illustrated in )LJXUH. It is the number of instruction cycles required between the time the request is sent and the time the first instruction located at the interrupt vector location enters the pipeline. 1RWH 7KHLQVWUXFWLRQSRLQWHUYDOXHVWDFHGDIWHUD0$&8QLW,QWHUUXSWGRHVQRWSRLQWWR WKHLQVWUXFWLRQWKDWWULJJHUHGWKHLQWHUUXSW7KHUHIRUHLWLVQRWSRVVLOHWRVSHFLI\ H[DFWO\WKHHQWU\SRLQWRIWKHLQWHUUXSW)XUWKHUPRUHGXHWRWKHLQWHUUXSWUHVSRQVH WLPHLWPD\QRWHSRVVLOHWRGHWHUPLQHWKHVRXUFHRIWKHLQWHUUXSWUHTXHVWVLQFH WKHVWDWXVRIIODJV&69(RU6/PD\KDYHFKDQJHGRQFHWKHLQWHUUXSWURXWLQH KDVVWDUWHG 166S V1 MA, User s Manual -16- V 1.0,

23 MA Unit Interrupt Response Time )(7& I1 I2 '(&2'( TRAP (1) TRAP (2) I1 (;(&87( TRAP (1) TRAP (2) :5,7(%$& TRAP (1) MA Interrupt Request )LJXUH 3LSHOLQH'LDJUDPIRU0$&8QLW,QWHUUXSW5HVSRQVH7LPH 166S V1 MA, User s Manual -17- V 1.0,

24 5 MA Unit Register Set User s Manual MA Unit Register Set All MA Unit registers are mapped into the SFR/SFR memory space. Registers can be accessed using the regular instruction set and the co-processor instruction called ostor. The following sections list the MA Unit registers and their corresponding SFR/SFR addresses. 1RWH :LWK &38 &RUH 6)5V DQ\ ULWH RSHUDWLRQ LWK WKH UHJXODU LQVWUXFWLRQ VHW WR D VLQJOH\WHRID0$&6)5FOHDUVWKHQRQDGGUHVVHGFRPSOHPHQWDU\\WHLWKLQ WKH VSHFLILHG 6)5 1RQLPSOHPHQWHG 6)5 LWV FDQQRW H PRGLILHG DQG DOD\V VXSSO\DUHDGYDOXHRI 166S V1 MA, User s Manual -18- V 1.0,

25 5.1 MA Unit Address Registers User s Manual MA Unit Register Set The double indirect addressing modes require additional ()SFRs: 2 address pointers IDX0/IDX1 and 4 offset registers QX0/QX1 and QR0/QR1. The address pointer registers IDX0 and IDX1 are located in the SFR space.,';))kk 6)5 5HVHW9DOXHK,';))$KK 6)5 5HVHW9DOXHK ,';L rw r )LHOG %LWV 7\SH,';L [15:1] rw 0RGLILDOHSRUWLRQRIDGGUHVVSRLQWHU [0] r As IDXi may only contain even values, bit 0 is fixed to zero. The offset registers QX0, QX1, QR0, and QR1 are located in the SFR space. 4;)KK (6)5 5HVHW9DOXHK 4;)KK (6)5 5HVHW9DOXHK 45)KK (6)5 5HVHW9DOXHK 45)KK (6)5 5HVHW9DOXHK ;L45L rw r )LHOG %LWV 7\SH 45L4;L [15:1] rw 0RGLILDOHSRUWLRQRIRIIVHWUHJLVWHUV Specifies 16-bit address offset for IDXi pointers (QXi) or GPR pointers (QRi). [0] r As MA Unit instructions handle word operands only, bit 0 is fixed to S V1 MA, User s Manual -19- V 1.0,

26 5.2 Accumulator Registers User s Manual MA Unit Register Set The 40-bit accumulator consists of the registers MAL, MAH and the low byte of MSW, which is described in &KDSWHU. MAL and MAH are located in the non bit-addressable SFR space. 0$+)((K)K 6)5 5HVHW9DOXHK $+ rw )LHOG %LWV 7\SH 0$+ [15:0] rw 0$&8QLW$FFXPXODWRU+LJK:RUG ontains bits 31 to 16 of the 40-bit MA Unit Accumulator. 0$/)(&K(K 6)5 5HVHW9DOXHK $/ rwh )LHOG %LWV 7\SH 0$/ [15:0] rwh 0$&8QLW$FFXPXODWRU/R:RUG ontains bits 15 to 0 of the 40-bit MA Unit Accumulator. 1RWH 0$/LVDXWRPDWLFDOO\FOHDUHGKHQ0$+LVULWWHQ\UHJXODU6)5DGGUHVVLQJ 166S V1 MA, User s Manual -20- V 1.0,

27 5.3 MA Unit Status Word (MSW) User s Manual MA Unit Register Set The bit-addressable register MSW reflects the current state of the MA Unit. It is located in the SFR space and includes the 8-bit accumulator extension MA and the 7 additional flags as shown below. 06:))'(K()K 6)5 5HVHW9DOXHK ,5 6/ ( 69 & = 1 0$($&&8([WHQVLRQ rwh - rwh rwh rwh rwh rwh rwh rwh )LHOG %LWV 7\SH 0$( [7:0] rwh $&&8([WHQVLRQ The eight most significant bits of the 40-bit MA Unit accumulator. 1 [8] rwh 1HJDWLYH5HVXOW)ODJ 0 MA Unit result is negative 1 MA Unit result is positive = [9] rwh =HUR)ODJ 0 MA Unit result is not zero 1 MA Unit result is zero & [10] rwh &DUU\)ODJ 0 o carry/borrow produced 1 arry/borrow produced 69 [11] rwh 6WLF\2YHUIOR)ODJ 0 o 40-bit overflow occurred 1 40-bit overflow occurred ( [12] rwh ([WHQVLRQ)ODJ 0 MA does not contain significant bits 1 MA contains significant bits 6/ [13] rwh 6WLF\/LPLW)ODJ 0 o automatic 32-bit saturation occurred 1 Automatic 32-bit saturation occurred 0,5 [15] rwh 0$&8QLW,QWHUUXSW5HTXHVW)ODJ 0 o MA Unit interrupt is requested 1 MA Unit interrupt is requested 166S V1 MA, User s Manual -21- V 1.0,

28 MA Unit Register Set $&&8([WHQVLRQ0$( These 8 bits are part of the 40-bit accumulator register. The MA Unit implicitly uses these bits during a MA Unit operation. When writing to MAH by regular SFR addressing, MA is automatically sign extended with the most significant bit of MAH and MAL is cleared. 1HJDWLYH5HVXOW)ODJ1 The flag is set if the most significant bit of the accumulator equals 1, otherwise it is cleared. With integer operations, the Flag can be interpreted as the sign bit of the MA Unit Accumulator (=1 for negative, =0 for positive). egative numbers are always represented as the 2 s complementation of the corresponding positive. =HUR)ODJ= The flag is set if the content of the MA Unit Accumulator is equal to zero, otherwise it is cleared. &DUU\)ODJ& After a MA Unit addition, the flag indicates that a carry from the accumulator s most significant bit (bit 7 of MA) has been generated. After a MA Unit subtraction, the flag indicates a "Borrow", which represents the logical negation of a "arry" for the addition. During a subtraction, the flag is set, if QR carry from the most significant bit of the accumulator has been generated. Subtraction is performed by the MA Unit as a 2 s complement addition and the flag is cleared when this complement addition caused a "arry". For left shift operations, the flag represents the value of the bit shifted out last. Right shift operations always clear the flag. 6WLF\2YHUIOR)ODJ69 The flag indicates an arithmetic overflow. The flag is set if, during a MA Unit operation, the accumulator exceeds the maximum range of 40-bit signed numbers. In the case of signed arithmetic, the flag is set if the carry into the sign bit differs from the carry out of the sign bit. With a left shift operation, the flag is set if the last bit shifted out is different from the new flag. If the flag is set then the result of the MA Unit operation is invalid. Once set, other MA Unit operations cannot affect the status of the flag. Only a direct write operation can clear it. ([WHQVLRQ)ODJ( The flag is set if the accumulator extension MA contains significant bits, i.e., if the highest 9 bits of the accumulator are not identical. 166S V1 MA, User s Manual -22- V 1.0,

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