MC14500B SEMICONDUCTOR TECHNICAL DATA

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1 SEIONDUTOR TEHNIAL DATA The 14B Industrial ontrol Unit (IU) is a single bit OS processor. The IU is designed for use in systems requiring decisions based on successive single bit information. An external RO stores the control program. With a program counter (and output latches and input multiplexers, if required) the IU in a system forms a stored program controller that replaces combinatorial logic. Applications include relay logic processing, serial data manipulation and control. The IU also may control an PU or be controlled by an PU. 16 D to 1. Hz Operation at VDD = 5 V On hip lock (Oscillator) Executes One Instruction per lock ycle 3 to 1 V Operation Low Quiescent urrent haracteristic of OS Devices apable of Driving One Low Power Schottky Load or Two Low Power TTL Loads over Full Temperature Range BLOK DIAGRA L SUFFIX ERAI ASE 62 P SUFFIX PLASTI ASE 64 DW SUFFIX SOI ASE 751G ORDERING INFORATION 14XXXBP 14XXXBL 14XXXBDW Plastic eramic SOI TA = 55 to 125 for all packages. DATA X2 I I1 I2 I3 RST 3 IEN D OS INST REG LU D RESULT REG. () D OEN STO STO UX + V 2 WRITE 16 V DD V SS 12 JP 11 RTN FLAG O 9 FLAG F PIN ASSIGNENT RST 1 16 VDD WRITE 2 DATA 3 14 I X2 I JP I RTN I 7 FLAG O VSS 9 FLAG F OSILLATOR OUTPUT X2 OSILLATOR INPUT REV 3 1/94 14B otorola, Inc OTOROLA OS LOGI DATA

2 Î Î Î AXIU RATINGS* (Voltages Referenced to VSS) Î Symbol Parameter Value Unit This device contains protection circuitry to VDD D Supply Voltage ÎÎ.5 to + 1. V guard against damage due to high static Vin, Vout Input or Output Voltage (D or Transient).5 to VDD +.5 V voltages or electric fields. However, precautions must be taken to avoid applications of Iin, Iout Input or Output urrent (D or Transient), ÎÎ ± ma any voltage higher than maximum rated volt- ÎÎ per Pin ages to this high impedance circuit. For proper PD Power Dissipation, per Package ÎÎ mw operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Tstg Storage Temperature ÎÎ 65 to + Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS TL Lead Temperature ( Second Soldering) ÎÎ 26 Î or VDD). Unused outputs must be left open. * aximum Ratings are those values beyond which damage to the device may occur. ÎÎ ÎÎ Temperature Derating: Plastic P and D/DW Packages: 7. mw/ From 65 To 125 ÎÎ eramic L Packages: 12 mw/ From To 125 ELETRIAL HARATERISTIS (Voltages Referenced to VSS) ÎÎ VDD ÎÎ haracteristic Symbol Î in ax in Typ # ax in ax Unit ÎÎ Output Voltage Level VOL Vin = VDD or ÎÎ.5 ÎÎ Level VOH Vin = or VDD ÎÎ Input Voltage Level Î VIL ÎÎ RST, D, X2 (VO = 4.5 or.5 ) ÎÎ (VO = 9. or 1. ) (VO = 13.5 or 1.5 ) ÎÎ 4. 1 Level ÎÎ VIH (VO =.5 or 4.5 ) (VO = 1. or 9. ) (VO = 1.5 or 13.5 ) Input Voltage # Level ÎÎ I, I1, I2, I3 VIL ÎÎ (VO = 4.5 or.5 ) (VO = 9. or 1. ) (VO = 13.5 or 1.5 ) ÎÎ 1 Level VIH (VO =.5 or 4.5 ) ÎÎ (VO = 1. or 9. ) (VO = 1.5 or 13.5 ) ÎÎ Output Drive urrent Source IOH madc Data, Write ÎÎ (VOH = 4.6 ) ÎÎ (VOH = 9.5 ) 3.6 (VOH = 13.5 ) (VOL =.4 ) Sink IOL madc ÎÎ (VOL =.5 ) ÎÎ (VOL = 1.5 ) ÎÎ Output Drive urrent Source IOH madc Other Outputs (VOH = 2.5 ) (VOH = 4.6 ) (VOH = 9.5 ) (VOH = 13.5 ) ÎÎ.9 ÎÎ 2.4 ÎÎ (VOL =.4 ) Sink IOL madc ÎÎ (VOL =.5 ) (VOL = 1.5 ) ÎÎ ÎÎ ÎÎ #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. OTOROLA OS LOGI DATA 14B 37

3 ÎÎ ÎÎ ÎÎ ELETRIAL HARATERISTIS continued (Voltages Referenced to VSS) ÎÎ VDD haracteristic Symbol ÎÎ Î in ax in Typ # ax ÎÎ in ax Unit Input urrent, RST Iin 25 ÎÎ µadc ÎÎ Input urrent Iin ±.1 ±.1 ±.1 ± 1. µadc Input apacitance (Data) in ÎÎ pf Input apacitance (All Other Inputs) in 7.5 ÎÎ pf Quiescent urrent IDD.5 µadc ÎÎ ÎÎ ÎÎ (Per Package) Iout = µa, Vin = or VDD ÎÎ 6 **Total Supply urrent at an IT ÎÎ External Load apacitance (L) ÎÎ IT = (1.5 µa/khz) f + IDD µadc ÎÎ IT = (3. µa/khz) f + IDD on All Outputs IT = (4.5 µa/khz) f + IDD ** The formulas given are for the typical characteristics only at 25. ÎÎ #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. ÎÎ SWITHING HARATERISTIS* (TA = 25 ; tr = tf = 2 ns for X and I inputs; L = 5 pf for JP,,, Flag O, Flag F; ÎÎ L = 13 pf + 1 TTL load for Data and Write.) ÎÎ All Types VDD haracteristic Symbol ÎÎ in Typ # ax Unit Propagation Delay Time, to tplh, Î ns tphl 125 to Flag F, Flag O, RTN, JP Î to Write Î to Data Î RST to Î 125 RST to Î 45 Note 1 RST to Flag F, Flag O, RTN, JP Î RST to Write, Data Î lock Pulse Width, tw(cl) Î 4 ns 1 Î 9 Rent Pulse Width, RST tw(r) Î ns 125 Î Setup Time Instruction tsu(l) Î 4 ns Data tsu(d) Î 5 4 Hold Time Instruction th(l) Î ns 5 5 Data th(d) Î 5 5 NOTE 1. aximum Reset Delay may extend to one half clock period. ÎÎ #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. 14B 3 OTOROLA OS LOGI DATA

4 f lk, LOK FREQUENY (Hz) 1 k k Î Î Î Î Pin No. Function Symbols Î Î 1 hip Reset RST 2 Î Write Pulse Î Write 3 4 Î Data In/Out SB Instruction Word Î Data I Î Bit 2 Instruction Word Î Bit 1 Instruction Word LSB Instruction Word Î I2 Î I1 I 9 Î Negative Supply (Ground) Î Flag on NOP F Flag on NOP O Î VSS Î Flag F Flag O Î Subroutine Return Flag Î Jump Instruction Flag Oscillator Input Î RTN Î JP X2 R, LOK FREQUENY RESISTOR 14 Î Oscillator Output Î 16 Î Result Register Positive Supply Î VDD ÎÎ Î Table 1. 14B Instruction Set ÎÎ Î Instruction ode nemonic Action ÎÎ Î NOPO No change in registers., Flag O Î LD LD AND Load result register. Data Load complement. Data Logical AND. Data Î AND OR OR Logical AND complement. Data Logical OR. + Data Logical OR complement. + Data Î XNOR Î STO STO Exclusive NOR. If = Data, 1 Store. Data Pin, Write Store complement. Data Pin, Write A Î IEN Input enable. Data IEN Register B 11 1 Î OEN JP Output enable. Data OEN Register Jump. JP Flag D E 11 F 11 Î RTN 1111 Î SKZ Return. RTN Flag and skip next instruction Skip next instruction if = NOPF No change in registers., Flag F kω kω 1 Ω Figure 1. Typical lock Frequency versus Resistor (R) ADDITIONAL OUTPUT DEVIES EORY I/O ADDRESS 14599B BIT ADDRESSABLE LATH WITH BIDIRETIONAL DATA OUTPUTS 4 BIT OP ODE HANNEL DATA SELETOR INPUTS TO PERIPHERAL DEVIES EORY ADDRESS I, I1, I2, I3 DATA BUS ADDITIONAL INPUT DEVIES PROGRA OUNTER LOK 14B IU DATA Figure 2. Outline of a Typical Organization for a 14B Based System OTOROLA OS LOGI DATA 14B 39

5 TIING WAVEFORS NOPO, NOPF, IEN, OEN remain unaffected RST IEN REGISTER OEN REGISTER tw(r) tphl (RESET TO XI) 4 BIT INSTRUTION tphl (RESET TO ) NOP NOPF NOPO FLAG FLAG F tplh (DATA TO FLAG) tphl SKZ, JP, RTN, IEN, OEN remain unaffected 4 BIT INSTRUTION RST tw(cl) SKZ * JP RTN * JP JP FLAG RTN FLAG tphl (RESET TO JUP) SKP F/F INTERNAL * Ignored. 14B 3 OTOROLA OS LOGI DATA

6 TIING WAVEFORS STO, STO, OEN 4 BIT INSTRUTION DATA OEN REGISTER (INTERNAL) STO ÉÉÉÉÉÉ ÉÉÉÉÉÉ STO ÉÉÉÉÉÉ 1 ÉÉÉÉÉÉ STO STO NOP OEN STO STO tplh, tphl ( TO DATA) WRITE tphl tplh VALID WHEN RST = L NOTE 1. Valid output data. LD, LD, AND, AND OR, OR, XNOR, IEN 4 BIT INSTRUTION LD, etc. tsu(i) NOP IEN LD, etc. th(i) DATA tsu(d) th(d) tplh, tphl ( TO ) IEN REGISTER (INTERNAL) VALID WHEN RST = L OTOROLA OS LOGI DATA 14B 311

7 OUTLINE DIENSIONS L SUFFIX ERAI DIP PAKAGE ASE 62 ISSUE V T SEATING PLANE F A E G D 16 PL.25 (.) T N B A S K L J 16 PL.25 (.) T B S NOTES: 1. DIENSIONING AND TOLERANING PER ANSI Y14.5, ONTROLLING DIENSION: INH. 3. DIENSION L TO ENTER OF LEAD WHEN FORED PARALLEL. 4. DIENSION F AY NAOW TO.76 (.3) WHERE THE LEAD ENTERS THE ERAI BODY. INHES ILLIETERS DI IN AX IN AX A B D E.5 BS 1.27 BS F G. BS 2.54 BS H K L.3 BS 7.62 BS N P SUFFIX PLASTI DIP PAKAGE ASE 64 ISSUE R 16 H A 1 G F 9 D 16 PL B S K.25 (.) T SEATING T PLANE A J L NOTES: 1. DIENSIONING AND TOLERANING PER ANSI Y14.5, ONTROLLING DIENSION: INH. 3. DIENSION L TO ENTER OF LEADS WHEN FORED PARALLEL. 4. DIENSION B DOES NOT INLUDE OLD FLASH. 5. ROUNDED ORNERS OPTIONAL. INHES ILLIETERS DI IN AX IN AX A B D F G. BS 2.54 BS H.5 BS 1.27 BS J K L S B 312 OTOROLA OS LOGI DATA

8 OUTLINE DIENSIONS DW SUFFIX PLASTI SOI PAKAGE ASE 751G 2 ISSUE A A X D 14X G B. (.25) T A S B S K X P T SEATING PLANE. (.25) J F B R X 45 NOTES: 1. DIENSIONING AND TOLERANING PER ANSI Y14.5, ONTROLLING DIENSION: ILLIETER. 3. DIENSIONS A AND B DO NOT INLUDE OLD PROTRUSION. 4. AXIU OLD PROTRUSION. (.6) PER SIDE. 5. DIENSION D DOES NOT INLUDE DABAR PROTRUSION. ALLOWABLE DABAR PROTRUSION SHALL BE.13 (.5) TOTAL IN EXESS OF D DIENSION AT AXIU ATERIAL ONDITION. ILLIETERS INHES DI IN AX IN AX A B D F G 1.27 BS.5 BS J K P R otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in otorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any license under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use otorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: otorola Literature Distribution; JAPAN: Nippon otorola Ltd.; Tatsumi SPD JLD, 6F Seibu Butsuryu enter, P.O. Box 2912; Phoenix, Arizona or Tatsumi Koto Ku, Tokyo 135, Japan FAX: TOUHTONE ASIA/PAIFI: otorola Semiconductors H.K. Ltd.; B Tai Ping Industrial Park, INTERNET: NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong OTOROLA OS LOGI DATA 14B/D 313

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