The Digital Logic Level. Chapter 3
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1 The Digital Logic Level Chapter 3
2 Gates and Boolean Algebra (1) Figure 3-1. (a) A transistor inverter. (b) A NAND gate. (c) A NOR gate.
3 Gates and Boolean Algebra (2) Figure 3-2. The symbols and functional behavior for the five basic gates.
4 Boolean Algebra (b) Figure 3-3. (a) The truth table for the majority function of three variables. (b) A circuit for (a).
5 Implementation of Boolean Functions Write truth table for function Provide inverters to generate complement of each input Draw AND gate for each term with 1 in result column Wire AND gates to appropriate inputs Feed output of all AND gates into an OR gate
6 Circuit Equivalence (1) Figure 3-4. Construction of (a) NOT, (b) AND, and (c) OR gates using only NAND gates or only NOR gates.
7 Circuit Equivalence (2) Figure 3-5. Two equivalent functions. (a) AB + AC
8 Circuit Equivalence (3) Figure 3-5. Two equivalent functions. (b) A(B + C).
9 Circuit Equivalence (4) Figure 3-6. Some identities of Boolean algebra.
10 Circuit Equivalence (5) Figure 3-7. Alternative symbols for some gates: (a) NAND (b) NOR (c) AND (d) OR
11 Circuit Equivalence (6) Figure 3-8. (a) The truth table for the XOR function. (b) (d) Three circuits for computing it.
12 Circuit Equivalence (7) Figure 3-9. (a) Electrical characteristics of a device. (b) Positive logic. (c) Negative logic.
13 Integrated Circuits Figure Common types of integrated-circuit packages, including a dual-inline package (a), pin grid array (b), and land grid array (c).
14 Multiplexers (1) Figure An eight-input multiplexer circuit.
15 Multiplexers (2) Figure (a) An eight-input multiplexer. (b) The same multiplexer wired to compute the majority function.
16 Decoders Figure A 3-to-8 decoder circuit.
17 Comparators Figure A simple 4-bit comparator.
18 Arithmetic Circuits (1) Figure A 1-bit left/right shifter.
19 Arithmetic Circuits (2) Figure (a) Truth table for 1-bit addition. (b) A circuit for a half adder.
20 Arithmetic Circuits (3) Figure (a) Truth table for full adder. (b) Circuit for a full adder.
21 Arithmetic Logic Units (1) Figure A 1-bit ALU.
22 Arithmetic Logic Units (2) Figure Eight 1-bit ALU slices connected to make an 8-bit ALU. The enables and invert signals are not shown for simplicity.
23 Clocks Figure (a) A clock. (b) The timing diagram for the clock. (c) Generation of an asymmetric clock.
24 Latches Figure (a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR.
25 Clocked SR Latches Figure A clocked SR latch.
26 Clocked D Latches Figure A clocked D latch.
27 Flip-Flops (1) Figure (a) A pulse generator. (b) Timing at four points in the circuit.
28 Flip-Flops (2) Figure A D flip-flop.
29 Flip-Flops (3) Figure D latches and flip-flops.
30 Memory Organization (1) Figure An 8-bit register constructed from single-bit flip-flops.
31 Memory Organization (2a) Figure Logic diagram for a 4 x 3 memory. Each row is one of the four 3-bit words. A read or write operation always reads or writes a complete word.
32 Memory Organization (2b) Figure Logic diagram for a 4 x 3 memory. Each row is one of the four 3-bit words. A read or write operation always reads or writes a complete word.
33 Memory Organization (3) Figure (a) A noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting buffer.
34 Memory Chips (1) Figure Two ways of organizing a 4-Mbit memory chip.
35 Memory Chips (2) Figure Two ways of organizing a 512-Mbit memory chip.
36 Nonvolatile Memory Chips(2) Figure A comparison of various memory types.
37 Field-Programmable Gate Arrays Figure (a) A field-programmable logic array lookup table (LUT). (b) The LUT configuration to create a 3-bit clearable counter.
38 CPU Chip Control Pins Bus control Interrupts Bus arbitration Coprocessor signaling Status Miscellaneous
39 CPU Chips Figure The logical pinout of a generic CPU. The arrows indicate input signals and output signals. The short diagonal lines indicate that multiple pins are used. For a specific CPU, a number will be given to tell how many.
40 Computer Buses (1) Figure A computer system with multiple buses.
41 Computer Buses (2) Figure Examples of bus masters and slaves.
42 Bus Width Figure Growth of an address bus over time.
43 Synchronous Buses (1) Figure (a) Read timing on a synchronous bus.
44 Synchronous Buses (2) Figure (b) Specification of some critical times.
45 Asynchronous Buses Figure Operation of an asynchronous bus.
46 Four Events of Full-Handshake
47 Bus Arbitration (1) Figure (a) A centralized one-level bus arbiter using daisy chaining. (b) The same arbiter, but with two levels.
48 Bus Arbitration (2) Figure Decentralized bus arbitration
49 Bus Operations (1) Figure A block transfer.
50 Bus Operations (2) Figure Use of the 8259A interrupt controller
51 The Intel Core i7 Figure The Core i7 physical pinout.
52 The Core i7 s Logical Pinout Figure Logical pinout of the Core i7.
53 Pipelining on Core i7 s DDR3 Memory Bus Three steps of memory requests Activate phase opens DRAM memory row, ready for access Read or Write phase multiple accesses can be made to individual words Precharge phase closes DRAM memory row, prepare for next activate
54 Pipelining Figure Pipelining memory requests on the Core i7 s DDR3 interface.
55 Texas Instruments OMAP4430 System-on-a-Chip (1) Figure The internal organization of the OMAP4430 system-on-a-chip.
56 Texas Instruments OMAP4430 System-on-a-Chip (2) Figure The OMAP4430 system-on-a-chip pinout.
57 Atmel ATmega168 Microcontroller (1) Figure Physical pinout of the ATmega168.
58 Atmel ATmega168 Microcontroller (2a) Figure The internal architecture and logical pinout of the ATmega168 are shown in Internal architecture and logical pinout of the ATmega168.
59 Atmel ATmega168 Microcontroller (2b) Figure The internal architecture and logical pinout of the ATmega168 are shown in Internal architecture and logical pinout of the ATmega168.
60 The PCI Bus (1) Figure Architecture of an early Pentium system. The thicker buses have more bandwidth than the thinner ones but the figure is not to scale.
61 The PCI Bus (2a) Figure The bus structure of a modern Core i7 system.
62 The PCI Bus (2b) Figure The bus structure of a modern Core i7 system.
63 PCI Bus Arbitration Figure The PCI bus uses a centralized bus arbiter.
64 PCI Bus Signals (1) Figure (a) Mandatory PCI bus signals.
65 PCI Bus Signals (2) Figure (b) Optional PCI bus signals.
66 PCI Bus Transactions Figure Examples of 32-bit PCI bus transactions. The first three cycles are used for a read operation, then an idle cycle, and then three cycles for a write operation.
67 The PCI Express Architecture Figure A typical PCI Express system.
68 The PCI Express Protocol Stack (1) Figure (a) The PCI Express protocol stack. (b) The format of a packet.
69 The PCI Express Protocol Stack (2) Each transaction uses 1 of 4 address spaces: Memory space for ordinary reads and writes) I/O space (for addressing device registers) Configuration space for system initialization, etc.) Message space for signaling, interrupts, etc.)
70 The Universal Serial Bus (1) Goals of USB developers: Users must not have to set switches or jumpers Users must not have to open the case to install new devices There should be only one kind of cable I/O devices should get power from the cable Up to 127 devices should be attachable to a single computer The system should support real-time devices (e.g., sound) Devices should be installable while the computer is running No reboot should be needed after installing a new device The bus and devices should be inexpensive to manufacture
71 The Universal Serial Bus (2) Figure The USB root hub sends out frames every 1.00 msec.
72 I/O Interfaces Figure A 24-bit PIO Interface.
73 Address Decoding Figure Location of the EPROM, RAM, and PIO in our 64-KB address space
74 End Chapter 3
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