CS152A / EE116L. LAB 1: Introduction to the Breadboard, Wiring, and 7400 Logic Chips

Transcription

1 CS152A / EE116L LAB 1: Introduction to the Breadboard, Wiring, and 7400 Logic Chips Purpose: This experiment is an introduction to components and equipment used throughout the term. Introduction: You will check an experiment board ("Breadboard"), check the action of several IC chips, design and build a simple sequential circuit. You will also learn how to create a clean clock signal that will be heavily used in future. Part 1: The Breadboard This device consists of three major parts: a ProtoBoard (Global Specialties PB- 105), an Altera UP-1 EPLD Experimenter's Board and a PC Interface Board (now used only for its four SPDT switches). The Altera UP-1 Board: This board is mounted at the upper right of the Experiment Board. It contains a number of switches, indicator lights, connectors and two Complex Programmable Devices. For the Lab 1 we will use only the indicator lights and the IC switches at the right edge of the board. Check the circuit diagrams for the connections. Note that the indicator lights will illuminate when a LOW voltage is applied to their input pins. The PC Interface Board: This device was designed to operate with a PC DOS program. It is to be connected to the PC parallel port via a ribbon cable. The board provides connections to the PC parallel port for outputting 8 bits of data from the PC to the Interface board, for inputting 8 bits of data to the PC, a CLOCK connection, and power for your experiment. The DOS software is no longer available, and this board is now used only for the four Single Pole Double Throw (SPDT) switches on the left side of this board. Note that VCC and Ground are provided on banana terminals. Use these connections for powering your ICs, which you will wire on the breadboard area. The source of the power for your connections (VCC and GND) is brought from the Altera Board. Since the PC power supply needs to be protected from wiring errors, such as direct shorts, the VCC power is fused. If no power is available, check for a blown fuse. There are three multi-pin connectors on this board. Connections to the PC were through the top connector, used for an 80-pin ribbon cable. This cable connection is not used in our lab experiments any more. The second connector block from the top has connections, to four SPDT pushbutton switches. The connections are (numbered left to right): Switch 1 (top): Pin 2 is the Center Pin; Pin 1 is Normally Closed (NC), Pin 3 is Normally Open (NO). Pin 4 is not connected.

2 Switch 2 (left): Pin 6 is the Center Pin; Pin 5 is Normally Closed (NC), Pin 7 is Normally Open (NO). Pin 8 is not connected. Switch 3 (bottom): Pin 10 is the Center Pin; Pin 9 is Normally Closed (NC), Pin 11 is Normally Open (NO). Pin 12 is not connected. Switch 4 (right): Pin 14 is the Center Pin; Pin 13 is Normally Closed (NC), Pin 15 is Normally Open (NO). Pin 16 is not connected. Depressing the push buttons changes the NO, NC connections. The bottom connector has connections for PC-to-Board signals, and connectors for Board-to-PC signals (8 each.) This connector is not used in our lab experiments. The ProtoBoard: This unit consists of a great many connectors arranged so that IC wiring may be accomplished with SHORT lengths of wire. The basic unit is five connectors wired together, out of sight, under the white Nylon covering. The spacing of the receptacles is 0.1 inch, standard spacing for IC 7400-series chips. A depression groove between sets of 5-pin groups indicates where you can mount a standard chip so that it straddles the depressed groove; then you may make connections to each pin as required. Paralleling the groove, at the sides of the Nylon blocks, there are additional groups of connectors, which are usually used for power and ground distribution. Remember to connect the Power and Ground buses to the banana connectors on the Interface Board. Be careful with the polarity! The ProtoBoard is used for connecting various ICs for your experiments. Power to the Experiment Board is supplied from a 5VDC 1.5A power adaptor. The adaptor supplies power directly to the UP-1 board and to the banana terminals on the Experiment Board. Note that the +5V terminal is fused as a precaution. Notes: Part 2: 74xx Chips 1. You should check out the switch connections and verify that you have +5V power. 2. In this experiment you will be using 74XX chips. They need power to operate. Check power connections carefully BEFORE you apply power to the board (turn off the power switch or unplug the power adapter when you wire the chips.) 3. You should get a wire cutter/stripper to make your wiring connections. Keep your wires short. 4. You may use a Logic Probe to check logic levels in your circuits. A Logic Probe is a convenience in checking 7400 circuit chips; however, it is usually too clumsy to check Surface Mount connections (such as the connections to the FLEX chip on the Altera board.) 5. The lab experiments are designed so that you need not use a Logic Probe. The indicator lights on the UP-1 hoard can be used for checking the logic levels on the chips. Keep you wiring neat, so that you can easily follow them 6. Don't expect to have your circuits always work on the first try. Expect wiring errors, bad chips, loose connections and troubles with the breadboard (broken wires in the holes, and under tile holes). Usually anything that can go wrong will

3 do so, at the least expected moment, and while you arc trying to demonstrate your work. You will also find that this statement is optimistic. Be careful! 7. Trouble-shoot your work in pieces. A completed design is more difficult to check once it is completed. 8. Turn the power OFF when you wire your circuits. Have one lab partner do the wiring, the other to check the connections, BEFORE power is turned ON. (1) Turn OFF the power to your ProtoBoard. Take a 7432 chip, and install it on your board. Make the proper power connections. Power the board ON. Test the action of the chip, and complete the Truth Table. You need to test only one of the four identical gates on the chip. (2) Turn the power OFF. Install a 7400 chip, similar to what you did in (1). Complete the Truth Table as before. Again, you need to test only one of the four identical circuit parts. (3) Wire the following circuit, with a 7400 and a 7486: Measure the output values (HIGH or LOW, l or 0) and complete the truth Table What is the function of this circuit? (4) Test the action of a 7474 D-Flip-Flop. This can be done with the indicator lights on the Altera board, or with a Logic Probe. You need to test only one of the two identical circuits on the 7474 chip. Note the actions of the PRESET and CLEAR inputs. Are these synchronous or asynchronous functions? Note the action of the clock relative to input D. When is the Flip -Flop set? What happens if the inputs are changed during the LOW period of the CLOCK? What

4 happens if the inputs are changed during the HIGH period of the CLOCK? When is the value of DATA (i.e. the state of the input) captured by the 7474? Look at Sec. 8.3 of Ercegovac et al for a description of D Flip -Plops. What kind of device is the 7474 chip? (5) Design a circuit which has two inputs: a signs MOOD and a free-running CLOCK and produces an output HIGH when the MOOD changes polarity, Note that MOOD changes slowly, and the free running CLOCK runs much faster. In this experiment YOU are the free -running CLOCK and should put out several (many) pulses before yon change the polarit y of MOOD. In essence you are asked to build a "change of MOOD" detector. This detector is a sequential machine. There are two types of such machine: Mealy and Moore. Read the MAX+PLUSII Help files for Mealy and for Moore machines. What is/are the salient difference/s? Design one of each of these. You need to wire and test only one of your designs. Note on 74xx chips The 700 series of Digital Logic Chips are realizations using Dual In-Line Packaged circuits with standardized supply voltage (Vcc = nominal 5.V) and specified input/output electrical characteristics. There are many different realizations, differing in power consumption, propagation times, and drive capabilities. Basically each package is capable of supplying input current to (and take negative current from) TEN similar devices of the same family of circuits. An example is the 7404 Hex Inverter: Family Power Dissipation t p max t T max I in max I out max 7404 TTL 22ns 33ma 74L04 Low -Power TTL 60ns 3ma 74LS04 Low-Power Schottky 35mW 15ns -0.4/0.1 ma -0.4/8.0 ma 74S04 Schottky 4.5ns 54ma 74HC04 High-Speed CMOS 750mW 95ns ±1uA 25ma t p : Propagation time, Input to Output; t T :Output Transition Time When the 7404 part is used in MAX2PLUS, the logic function is used, and the electrica l characteristics (particularly t p ) is the basic gate timing of the Altera chip in the implemented design. Parts List: 7400 Quad 2-input NAND 7402 Quad 2-input NOR 7432 Quad 2 input OR 7474 Dual D-Flip-flop 7486 Quad 2-input XOR #24 AWG Insulated Hook-up Wire

5 Part 3: The Clean Clock Mechanical switches such as the ones used on the Alters UP-1 Board, do not provide a clean switching action. Instead of making or breaking a clean connection, they bounce. Hence, the contact is not a clean OFF/ON connection, but rather a series of brief contact connections that may last several milliseconds. See the copy of the attached report from lab measurements. Measured maximum duration of bounces of the switches on the UP-1 board were around 6 ms. Note that the circuitry in the FPGA operates in nanoseconds, hence great attention must be paid to provide switching signals for use in the FPGAs that have clean ON/OFF characteristics. Such a signal is called a "Clean Clock." There is a 25 MHz on-board clock on the UP-1 board. Events occurring with this signal are much too fast to be observed. Hence you will test your designs with clock signals that you operate manually. You must then haves Clean Clock. There are several ways to provide a Clean Clock signal. It is suggested that you use a clock signal produced with a Flip -flop whose output' is controlled from its asynchronous Clear and Set pins. Method 1: Use a 7474 D Flip-flop IC chip and a Single-Pole, Double -Throw Switch with Pull-up resistors. The asynchronous control pins CLEAR and SET of a flip-flop will set the output of the device into the LOW or HIGH voltage states they are momentarily connected to LOW. Since we use positive logic, HIGH corresponds to the supply voltage (+5V) and LOW is GROUND. An SPDT switch will transfer contact from a middle (input) contact to either of two output contacts. Of course, the contact being made will bounce as the switch mechanism moves. However, if the output contacts are wired to the CLEAR, and SET terminals of a flip -flop (in this case a D Flip-flop), then the output of the flop-flop will change once, depending on the momentary LOW voltage applied to either asynchronous terminal, and remains in its new state as long as no LOW s applied to the opposite asynchronous terminal. Hence normal switch bouncing is tolerated. Connect the center of the SPDT switch to GND and the outputs of the switch to SET and CLEAR. To assure a good HIGH value when the switch is not making a contact to either SET or CLEAR, use two resistors to connect SET and CLEAR to HIGH (+5 Volts). The value of this resistor is not critical. It must be larger than zero (else that will blow the fuse - why?) and less than infinity (that is tantamount to an open circuit for the default HIGH values). Any value from 2 k-ohms to 30 k-ohms is workable. Method 2: Use a 7474 D Flip-flop IC chip and a Single -Pole Double-Throw Switch without Pull-up resistors. The pull-up resistors MAY not be needed since the SET and CLEAR inputs of the 7474 chip should float to a HIGH value. You are now relying on the flip-flop internal circuit actions, which may be very slow. Method 3: Use a D Flip-flop in the FPGA chip and a Single -Pole Double-Throw Switch with Pull-up resistors. Essentially you replace the 7474 chip with a DFF inside the FPGA. A refinement would be to wire the DFF as a latch to hold the last output value. See the attached circuit diagrams.

6 Method 4: Use a D Flip-flop in the FPGA chip and a Single -Pole Double-Throw Switch without Pull-up resistors. This consists of omitting the external resistors. Again, you are relying on internal circuit parameters, as in Method 2, which may be too slow. Method 5: Use a counter in the FPGA chip and a Single-Pole, Single-Throw Switch with or without Pull-up resistors. A counter is started when the input: signal changes, and after a 10 ms delay the input is connected to the output. Using the 40 us clock on the UP-1 board, you need about 18 stages in your binary counter(why?). This method is shown in the Altera design examples, but it is a complex solution. However, it needs only a single-pole switch, such as the pushbutton switches on the UP-1 board.