Dual, Current Feedback Low Power Op Amp AD812

Transcription

1 a FEATURES Two Video Amplifiers in One -Lead SOIC Package Optimized for Driving Cables in Video Systems Excellent Video Specifications (R L = ): Gain Flatness. db to MHz.% Differential Gain Error. Differential Phase Error Low Power Operates on Single +3 V Supply. ma/amplifier Max Power Supply Current High Speed MHz Unity Gain Bandwidth (3 db) V/ s Slew Rate Easy to Use ma Output Current Output Swing to V of Rails ( Load) APPLICATIONS Video Line Driver Professional Cameras Video Switchers Special Effects PRODUCT DESCRIPTION The AD is a low power, single supply, dual video amplifier. Each of the amplifiers have ma of output current and are optimized for driving one back-terminated video load ( Ω) each. Each amplifier is a current feedback amplifier and features gain flatness of. db to MHz while offering differential gain and phase error of.% and.. This makes the AD ideal for professional video electronics such as cameras and video switchers. NORMALIZED GAIN db k M M M Figure. Fine-Scale Gain Flatness vs. Frequency, Gain = +, R L = Ω Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. G = + R L = Dual, Current Feedback Low Power Op Amp AD PIN CONFIGURATION -Lead Plastic Mini-DIP and SOIC OUT IN +IN V 3 + AD + 7 V+ OUT The AD offers low power of. ma per amplifier max (V S = + V) and can run on a single +3 V power supply. The outputs of each amplifier swing to within one volt of either supply rail to easily accommodate video signals of V p-p. Also, at gains of + the AD can swing 3 V p-p on a single + V power supply. All this is offered in a small -lead plastic DIP or -lead SOIC package. These features make this dual amplifier ideal for portable and battery powered applications where size and power is critical. The outstanding bandwidth of MHz along with V/µs of slew rate make the AD useful in many general purpose high speed applications where a single + V or dual power supplies up to ± V are available. The AD is available in the industrial temperature range of C to + C. DIFFERENTIAL PHASE Degrees DIFFERENTIAL GAIN IN +IN DIFFERENTIAL PHASE 9 3 Figure. Differential Gain and Phase vs. Supply Voltage, Gain = +, R L = Ω One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 7/39-7 World Wide Web Site: Fax: 7/3-73 Analog Devices, Inc., DIFFERENTIAL GAIN %

2 AD* Product Page Quick Links Last Content Update: // Comparable Parts View a parametric search of comparable parts Evaluation Kits Universal Evaluation Board for Dual High Speed Operational Amplifiers Documentation Application Notes AN-: Low Cost, Low Power Devices for HDSL Applications AN-9: Using the Analog Devices Active Filter Design Tool AN-9: Universal Precision Op Amp Evaluation Board AN-: A WiMax Double Downconversion IF Sampling Receiver Design Data Sheet AD: Dual, Current Feedback Low Power Op Amp Data Sheet User Guides UG-: Universal Evaluation Board for Dual High Speed Op Amps in SOIC Packages Tools and Simulations AD SPICE Macro-Model Reference Materials Tutorials MT-3: Current Feedback (CFB) Op Amps MT-: Current Feedback Op Amp Noise Considerations MT-7: High Speed Current Feedback Op Amps MT-9: Compensating for the Effects of Input Capacitance on VFB and CFB Op Amps Used in Current-to-Voltage Converters Design Resources AD Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all AD EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified.

3 AD SPECIFICATIONS Dual Supply T A = + C, R L =, unless otherwise noted) Model ADA Conditions V S Min Typ Max Units DYNAMIC PERFORMANCE 3 db Bandwidth G = +, No Peaking ± V MHz ± V 7 MHz Gain = + ± V MHz Bandwidth for. db Flatness G = + ± V 3 MHz ± V MHz Slew Rate G = +, R L = kω ± V 7 V/µs V Step ± V V/µs G =, R L = kω ± V V/µs ± V V/µs Settling Time to.% G =, R L = kω V O = 3 V Step ± V ns V O = V Step ± V ns NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion f C = MHz, R L = kω ± V 9 dbc Input Voltage Noise f = khz ± V, ± V 3. nv/ Hz Input Current Noise f = khz, +In ± V, ± V. pa/ Hz f = khz, In ± V, ± V pa/ Hz Differential Gain Error NTSC, G = +, R L = Ω ± V.. % ± V.. % Differential Phase Error ± V.7. Degrees ± V.. Degrees DC PERFORMANCE Input Offset Voltage ± V, ± V mv T MIN T MAX mv Offset Drift ± V, ± V µv/ C Input Bias Current ± V, ± V 7 µa T MIN T MAX 3 µa +Input Bias Current ± V, ± V.3. µa T MIN T MAX. µa Open-Loop Voltage Gain V O = ±. V, R L = Ω ± V 7 db T MIN T MAX 9 db V O = ± V, R L = kω ± V 7 db T MIN T MAX 7 db Open-Loop Transresistance V O = ±. V, R L = Ω ± V 3 kω T MIN T MAX 7 kω V O = ± V, R L = kω ± V kω T MIN T MAX 37 kω INPUT CHARACTERISTICS Input Resistance +Input ± V MΩ Input Ω Input Capacitance +Input.7 pf Input Common Mode ± V. ± V Voltage Range ± V 3. ± V Common-Mode Rejection Ratio Input Offset Voltage V CM = ±. V ± V db Input Current 3. µa/v +Input Current.7. µa/v Input Offset Voltage V CM = ± V ± V db Input Current. 3.3 µa/v +Input Current.. µa/v

4 Model ADA Conditions V S Min Typ Max Units OUTPUT CHARACTERISTICS Output Voltage Swing R L = Ω, T MIN T MAX ± V ± V R L = kω, T MIN T MAX ± V 3.. ± V Output Current ± V 3 ma ± V ma Short Circuit Current G = +, R F = 7 Ω ± V ma = V Output Resistance Open-Loop ± V Ω MATCHING CHARACTERISTICS Dynamic Crosstalk G = +, f = MHz ± V, ± V 7 db Gain Flatness Match G = +, f = MHz ± V. db DC Input offset Voltage T MIN T MAX ± V, ± V. 3. mv Input Bias Current T MIN T MAX ± V, ± V µa POWER SUPPLY Operating Range ±. ± V Quiescent Current Per Amplifier ± V 3.. ma ± V.. ma T MIN T MAX ± V. ma Power Supply Rejection Ratio Input Offset Voltage V S = ±. V to ± V 7 db Input Current.3. µa/v +Input Current.. µa/v NOTES Slew rate measurement is based on % to 9% rise time in the specified closed-loop gain. Specifications subject to change without notice. Single Supply (@ T A = + C, R L =, unless otherwise noted) Model ADA Conditions V S Min Typ Max Units DYNAMIC PERFORMANCE 3 db Bandwidth G = +, No Peaking + V 3 MHz +3 V 3 MHz Bandwidth for. db Flatness G = + + V 3 MHz +3 V MHz Slew Rate G = +, R L = kω + V V/µs +3 V V/µs AD NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = khz + V, +3 V 3. nv/ Hz Input Current Noise f = khz, +In + V, +3 V. pa/ Hz f = khz, In + V, +3 V pa/ Hz Differential Gain Error NTSC, G = +, R L = Ω + V.7 % G = + +3 V. % Differential Phase Error G = + + V. Degrees G = + +3 V. Degrees 3

5 AD SPECIFICATIONS Single Supply (Continued) ADA Model Conditions V S Min Typ Max Units DC PERFORMANCE Input Offset Voltage + V, +3 V.. mv T MIN T MAX 7. mv Offset Drift + V, +3 V 7 µv/ C Input Bias Current + V, +3 V µa T MIN T MAX 3 µa +Input Bias Current + V, +3 V.. µa T MIN T MAX. µa Open-Loop Voltage Gain V O = +. V p-p + V 7 73 db V O = +.7 V p-p +3 V 7 db Open-Loop Transresistance V O = +. V p-p + V kω V O = +.7 V p-p +3 V 3 kω INPUT CHARACTERISTICS Input Resistance +Input + V MΩ Input + V 9 Ω Input Capacitance +Input pf Input Common Mode + V.. V Voltage Range +3 V.. V Common-Mode Rejection Ratio Input Offset Voltage V CM =. V to 3.7 V + V db Input Current 3. µa/v +Input Current.. µa/v Input Offset Voltage V CM = V to V +3 V db Input Current 3. µa/v +Input Current. µa/v OUTPUT CHARACTERISTICS Output Voltage Swing p-p R L = kω, T MIN T MAX + V V p-p R L = Ω, T MIN T MAX + V. 3. V p-p +3 V..3 V p-p Output Current + V 3 ma +3 V ma Short Circuit Current G = +, R F = 7 Ω + V ma = V MATCHING CHARACTERISTICS Dynamic Crosstalk G = +, f = MHz + V, +3 V 7 db Gain Flatness Match G = +, f = MHz + V, +3 V. db DC Input offset Voltage T MIN T MAX + V, +3 V. 3. mv Input Bias Current T MIN T MAX + V, +3 V µa POWER SUPPLY Operating Range. 3 V Quiescent Current Per Amplifier + V 3.. ma +3 V ma T MIN T MAX + V. ma Power Supply Rejection Ratio Input Offset Voltage V S = +3 V to +3 V 7 db Input Current.3. µa/v +Input Current.. µa/v TRANSISTOR COUNT NOTES Slew rate measurement is based on % to 9% rise time in the specified closed-loop gain. Single supply differential gain and phase are measured with the ac coupled circuit of Figure 3. Specifications subject to change without notice.

6 AD ABSOLUTE MAXIMUM RATINGS Supply Voltage ± V Internal Power Dissipation Plastic (N) Watts Small Outline (R) Watts Input Voltage (Common Mode) ± V S Differential Input Voltage ±. V Output Short Circuit Duration Observe Power Derating Curves Storage Temperature Range N, R C to + C Operating Temperature Range C to + C Lead Temperature Range (Soldering, sec) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specification is for device in free air: -lead plastic package: θ JA = 9 C/Watt; -lead SOIC package: θ JA = C/Watt. ORDERING GUIDE Temperature Package Package Model Range Description Option ADAN C to + C -Lead Plastic DIP N- ADAR C to + C -Lead Plastic SOIC SO- ADAR-REEL 3" Reel ADAR-REEL7 7" Reel V+ METALIZATION PHOTO Dimensions shown in inches and (mm)..73 (.99) OUT 7 IN MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD is limited by the associated rise in junction temperature. The maximum safe junction temperature for the plastic encapsulated parts is determined by the glass transition temperature of the plastic, about C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 7 C for an extended period can result in device failure. While the AD is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature ( degrees) is not exceeded under all conditions. To ensure proper operation, it is important to observe the derating curves. It must also be noted that in high (noninverting) gain configurations (with low values of gain resistor), a high level of input overdrive can result in a large input error current, which may result in a significant power dissipation in the input stage. This power must be included when computing the junction temperature rise due to total internal power. MAXIMUM POWER DISSIPATION Watts.... -LEAD SOIC PACKAGE -LEAD MINI-DIP PACKAGE T J = + C +IN.39 (.37) AMBIENT TEMPERATURE C Figure 3. Plot of Maximum Power Dissipation vs. Temperature V OUT IN 3 +IN V CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

7 AD Typical Performance Characteristics COMMON-MODE VOLTAGE RANGE Volts Figure. Input Common-Mode Voltage Range vs. Supply Voltage TOTAL SUPPLY CURRENT ma V S = JUNCTION TEMPERATURE C Figure 7. Total Supply Current vs. Junction Temperature T A = + C OUTPUT VOLTAGE V p-p NO LOAD R L = TOTAL SUPPLY CURRENT ma 9 7 Figure. Output Voltage Swing vs. Supply Voltage Figure. Total Supply Current vs. Supply Voltage 3 OUTPUT VOLTAGE Volts p-p SUPPLY SUPPLY INPUT BIAS CURRENT A I B, I B, V S = +I B, V S =, k k LOAD RESISTANCE Figure. Output Voltage Swing vs. Load Resistance JUNCTION TEMPERATURE C Figure 9. Input Bias Current vs. Junction Temperature

8 AD INPUT OFFSET VOLTAGE mv V S = OUTPUT CURRENT ma 7 3 JUNCTION TEMPERATURE C Figure. Input Offset Voltage vs. Junction Temperature Figure 3. Linear Output Current vs. Supply Voltage k SHORT CIRCUIT CURRENT ma SINK SOURCE CLOSED-LOOP OUTPUT RESISTANCE. G = + S S JUNCTION TEMPERATURE C Figure. Short Circuit Current vs. Junction Temperature. k k M M M Figure. Closed-Loop Output Resistance vs. Frequency 3 7 OUTPUT CURRENT ma V S = OUTPUT VOLTAGE V p-p R L = k V S = 3 JUNCTION TEMPERATURE C Figure. Linear Output Current vs. Junction Temperature k M M M Figure. Large Signal Frequency Response 7

9 AD VOLTAGE NOISE nv/ Hz INVERTING INPUT CURRENT NOISE VOLTAGE NOISE NONINVERTING INPUT CURRENT NOISE CURRENT NOISE pa/ Hz TRANSIMPEDANCE db GAIN PHASE V S = V S = 9 3 PHASE Degrees k k k Figure. Input Current and Voltage Noise vs. Frequency k k M M M Figure 9. Open-Loop Transimpedance vs. Frequency (Relative to Ω) COMMON-MODE REJECTION db k k M M M V S = Figure 7. Common-Mode Rejection vs. Frequency HARMONIC DISTORTION dbc RD 3 k G = + V S = V p-p ; R L = k V S = ; R L = ND HARMONIC 3 RD HARMONIC ND V S = k k M M M Figure. Harmonic Distortion vs. Frequency POWER SUPPLY REJECTION db 7 3. OUTPUT SWING FROM V TO %.%.% GAIN = k k M M M Figure. Power Supply Rejection vs. Frequency 3 SETTLING TIME ns Figure. Output Swing and Error vs. Settling Time

10 AD R L = G = + G = + SLEW RATE V/ s G = + G = + G = SLEW RATE V/ s G = + G = G = OUTPUT STEP SIZE Vp-p Figure. Slew Rate vs. Output Step Size Figure. Maximum Slew Rate vs. Supply Voltage V ns mv ns 9 9 % % V mv Figure 3. Large Signal Pulse Response, Gain = +, (R F = 7 Ω, R L = Ω, V S = ± V) Figure. Small Signal Pulse Response, Gain = +, (R F = 7 Ω, R L = Ω, V S = ± V) CLOSED-LOOP GAIN db 3 PHASE GAIN G = + R L = 9 7 PHASE SHIFT Degrees 3dB BANDWIDTH MHz PEAKING G = + R L = db PEAKING.dB R F = 7 R F = Figure. Closed-Loop Gain and Phase vs. Frequency, G = + Figure 7. 3 db Bandwidth vs. Supply Voltage, G = + 9

11 AD mv ns mv ns 9 9 % % mv Figure. Large Signal Pulse Response, Gain = +, (R F = 37 Ω, R L = Ω, V S = ± V) Figure 3. Small Signal Pulse Response, Gain = +, (R F = 37 Ω, R L = Ω, V S = ± V) CLOSED-LOOP GAIN (NORMALIZED) db 3 PHASE GAIN G = + R L = 9 7 Figure 9. Closed-Loop Gain and Phase vs. Frequency, Gain = +, R L = Ω PHASE SHIFT Degrees CLOSED-LOOP GAIN (NORMALIZED) db 3 PHASE GAIN G = + R L = k Figure 3. Closed-Loop Gain and Phase vs. Frequency, Gain = +, R L = k Ω PHASE SHIFT Degrees 3dB BANDWIDTH MHz G = + R L = PEAKING R F = db R F = 37 R F = 9 3dB BANDWIDTH MHz G = + R L = k R F = R F = 37 R F = 9 Figure 3. 3 db Bandwidth vs. Supply Voltage, Gain = +, R L = Ω Figure db Bandwidth vs. Supply Voltage, Gain = +, R L = k Ω

12 AD V ns mv ns 9 9 % % V mv Figure 3. Large Signal Pulse Response, Gain =, (R F = 7 Ω, R L = Ω, V S = ± V) Figure 37. Small Signal Pulse Response, Gain =, (R F = 7 Ω, R L = Ω, V S = ± V) CLOSED-LOOP GAIN (NORMALIZED) db 3 PHASE GAIN G = R L = 9 7 Figure 3. Closed-Loop Gain and Phase vs. Frequency, Gain =, R L = Ω PHASE SHIFT Degrees CLOSED-LOOP GAIN (NORMALIZED) db 3 PHASE GAIN G = R L = k 7 Figure 3. Closed-Loop Gain and Phase vs. Frequency, Gain =, R L = kω 9 PHASE SHIFT Degrees 3dB BANDWIDTH MHz G = R L = PEAKING.dB PEAKING.dB R F = R F = 7 Figure 3. 3 db Bandwidth vs. Supply Voltage, Gain =, R L = Ω 3dB BANDWIDTH MHz G = R L = k R F = R F = 37 R F = 9 Figure db Bandwidth vs. Supply Voltage, Gain =, R L = kω

13 AD General Considerations The AD is a wide bandwidth, dual video amplifier which offers a high level of performance on less than. ma per amplifier of quiescent supply current. It is designed to offer outstanding performance at closed-loop inverting or noninverting gains of one or greater. Built on a low cost, complementary bipolar process, and achieving bandwidth in excess of MHz, differential gain and phase errors of better than.% and. (into Ω), and output current greater than ma, the AD is an exceptionally efficient video amplifier. Using a conventional current feedback architecture, its high performance is achieved through careful attention to design details. Choice of Feedback and Gain Resistors Because it is a current feedback amplifier, the closed-loop bandwidth of the AD depends on the value of the feedback resistor. The bandwidth also depends on the supply voltage. In addition, attenuation of the open-loop response when driving load resistors less than about Ω will affect the bandwidth. Table I contains data showing typical bandwidths at different supply voltages for some useful closed-loop gains when driving a load of Ω. (Bandwidths will be about % greater for load resistances above a few hundred ohms.) The choice of feedback resistor is not critical unless it is important to maintain the widest, flattest frequency response. The resistors recommended in the table are those (metal film values) that will result in the widest. db bandwidth. In those applications where the best control of the bandwidth is desired, % metal film resistors are adequate. Wider bandwidths can be attained by reducing the magnitude of the feedback resistor (at the expense of increased peaking), while peaking can be reduced by increasing the magnitude of the feedback resistor. Table I. 3 db Bandwidth vs. Closed-Loop Gain and Feedback Resistor (R L = Ω) V S (V) Gain R F ( ) BW (MHz) ± ± To estimate the 3 db bandwidth for closed-loop gains or feedback resistors not listed in the above table, the following two pole model for the AD many be used: G ACL = ( RF + GrIN) CT S S RF GrIN CT f + ( + ) + π where: A CL = closed-loop gain G = + R F /R G r IN = input resistance of the inverting input C T = transcapacitance, which forms the open-loop dominant pole with the tranresistance R F = feedback resistor R G = gain resistor f = frequency of second (nondominant) pole S = πj f Appropriate values for the model parameters at different supply voltages are listed in Table II. Reasonable approximations for these values at supply voltages not found in the table can be obtained by a simple linear interpolation between those tabulated values which bracket the desired condition. Table II. Two-Pole Model Parameters at Various Supply Voltages V S r IN ( ) C T (pf) f (MHz) ±. ± As discussed in many amplifier and electronics textbooks (such as Roberge s Operational Amplifiers: Theory and Practice), the 3 db bandwidth for the -pole model can be obtained as: f 3 = f N [ d + ( d + d ) / ] / where: and: f N f = ( R + Gr ) C F IN T / d = (/) [f (R F + Gr IN ) C T ] / This model will predict 3 db bandwidth within about to % of the correct value when the load is Ω. However, it is not an accurate enough to predict either the phase behavior or the frequency response peaking of the AD. Printed Circuit Board Layout Guidelines As with all wideband amplifiers, printed circuit board parasitics can affect the overall closed-loop performance. Most important for controlling the. db bandwidth are stray capacitances at the output and inverting input nodes. Increasing the space between signal lines and ground plane will minimize the coupling. Also, signal lines connecting the feedback and gain resistors should be kept short enough that their associated inductance does not cause high frequency gain errors.

14 AD Power Supply Bypassing Adequate power supply bypassing can be very important when optimizing the performance of high speed circuits. Inductance in the supply leads can (for example) contribute to resonant circuits that produce peaking in the amplifier s response. In addition, if large current transients must be delivered to a load, then large (greater than µf) bypass capacitors are required to produce the best settling time and lowest distortion. Although. µf capacitors may be adequate in some applications, more elaborate bypassing is required in other cases. When multiple bypass capacitors are connected in parallel, it is important to be sure that the capacitors themselves do not form resonant circuits. A small (say Ω) resistor may be required in series with one of the capacitors to minimize this possibility. As discussed below, power supply bypassing can have a significant impact on crosstalk performance. Achieving Low Crosstalk Measured crosstalk from the output of amplifier to the input of amplifier of the AD is shown in Figure. The crosstalk from the output of amplifier to the input of amplifier is a few db better than this due to the additional distance between critical signal nodes. A carefully laid-out PC board should be able to achieve the level of crosstalk shown in the figure. The most significant contributors to difficulty in achieving low crosstalk are inadequate power supply bypassing, overlapped input and/or output signal paths, and capacitive coupling between critical nodes. The bypass capacitors must be connected to the ground plane at a point close to and between the ground reference points for the two loads. (The bypass of the negative power supply is particularly important in this regard.) There are two amplifiers in the package, and low impedance signal return paths must be provided for each load. (Using a parallel combination of µf,. µf, and. µf bypass capacitors will help to achieve optimal crosstalk.) The input and output signal return paths must also be kept from overlapping. Since ground connections are not of perfectly zero impedance, current in one ground return path can produce a voltage drop in another ground return path if they are allowed to overlap. Electric field coupling external to (and across) the package can be reduced by arranging for a narrow strip of ground plane to be run between the pins (parallel to the pin rows). Doing this on both sides of the board can reduce the high frequency crosstalk by about db or db. Driving Capacitive Loads When used with the appropriate output series resistor, any load capacitance can be driven without peaking or oscillation. In most cases, less than Ω is all that is needed to achieve an extremely flat frequency response. As illustrated in Figure, the AD can be very attractive for driving largely capacitive loads. In this case, the AD s high output short circuit current allows for a V/µs slew rate when driving a pf capacitor. R G R T AD R F +V S. F V S. F. F. F Figure. Circuit for Driving a Capacitive Load R S C L R L V O CROSSTALK db R L = CLOSED-LOOP GAIN db V S = G = + R F = 7 R L = k C L = pf R S = R S = R S = 3 k M M Figure. Crosstalk vs. Frequency M Figure. Response to a Small Load Capacitor at ± V 3

15 AD G = + R F = 7 R L = k 9 V ns CLOSED-LOOP GAIN db C L = pf, R S = C L = pf, R S = 3 % V 9 Figure 3. Response to Large Load Capacitor, V S = ± V 9 % ns Figure. Pulse Response of Circuit of Figure with C L = pf, R L = kω, R F = R G = 7 Ω, R S = Ω Overload Recovery There are three important overload conditions to consider. They are due to input common mode voltage overdrive, input current overdrive, and output voltage overdrive. When the amplifier is configured for low closed-loop gains, and its input common-mode voltage range is exceeded, the recovery time will be very fast, typically under ns. When configured for a higher gain, and overloaded at the output, the recovery time will also be short. For example, in a gain of +, with db of input overdrive, the recovery time of the AD is about ns. Figure. db Overload Recovery; G =, R L = Ω, V S = ± V In the case of high gains with very high levels of input overdrive, a longer recovery time may occur. For example, if the input common-mode voltage range is exceeded in a gain of +, the recovery time will be on the order of ns. This is primarily due to current overloading of the input stage. As noted in the warning under Maximum Power Dissipation, a high level of input overdrive in a high noninverting gain circuit can result in a large current flow in the input stage. For differential input voltages of less than about. V, this will be internally limited to less than ma (decreasing with supply voltage). For input overdrives which result in higher differential input voltages, power dissipation in the input stage must be considered. It is recommended that external diode clamps be used in cases where the differential input voltage is expected to exceed. V. High Performance Video Line Driver At a gain of +, the AD makes an excellent driver for a backterminated 7 Ω video line. Low differential gain and phase errors and wide. db bandwidth can be realized over a wide range of power supply voltage. Outstanding gain and group delay matching are also attainable over the full operating supply voltage range. R G R F +V S. F 7 CABLE AD 7 7 CABLE 7 7. F V S Figure. Gain of + Video Line Driver (R F = R G from Table I)

16 AD CLOSED-LOOP GAIN db 3 PHASE GAIN G = + R L = FREQUENCY MHz Figure 7. Closed-Loop Gain and Phase vs. Frequency for the Line Driver PHASE SHIFT Degrees NORMALIZED GAIN db k M M G = + R L = M Figure. Fine-Scale Gain Flatness vs. Frequency, Gain = +, R L = Ω 3dB BANDWIDTH MHz 9 7 G = + R L = PEAKING db NO PEAKING R F = 9 R F = 7 R F = 7 GAIN MATCH db V S = R F = G = + R L = R F = Figure. 3 db Bandwidth vs. Supply Voltage, Gain = +, R L = Ω. Figure. Closed-Loop Gain Matching vs. Frequency, Gain = +, R L = Ω DIFFERENTIAL PHASE Degrees DIFFERENTIAL GAIN DIFFERENTIAL PHASE 9 3 Figure 9. Differential Gain and Phase vs. Supply Voltage, Gain = +, R L = Ω... DIFFERENTIAL GAIN % GROUP DELAY ns.... k DELAY DELAY MATCHING M M V S = TO M Figure. Group Delay and Group Delay Matching vs. Frequency, G = +, R L = Ω

17 AD Operation Using a Single Supply The AD will operate with total supply voltages from 3 V down to. V. With proper biasing (see Figure 3), it can be an outstanding single supply video amplifier. Since the input and output voltage ranges extend to within volt of the supply rails, it will handle a.3 V p-p signal on a single 3.3 V supply, or a 3 V p-p signal on a single V supply. The small signal,. db bandwidths will exceed MHz in either case, and the large signal bandwidths will exceed MHz. The capacitively coupled cable driver in Figure 3 will achieve outstanding differential gain and phase errors of.7% and. degrees respectively on a single V supply. Resistor R, in this circuit, is selected to optimize the differential gain and phase by operating the amplifier in its most linear region. To optimize the circuit for a 3 V supply, a value of kω is recommended for R. C F C3 3 F C F R 9k R.k 9 R3 k 9 AD +V S C OUT 7 F 7 7 CABLE 7 Figure 3. Biasing for Single Supply Operation.. (.9.). (3.) MIN..3 (. +.).39 (9.9) PIN. (.) BSC -Lead Plastic DIP (N-). (.3). (.). (.3).33 (.) NOM SEATING PLANE.3 (.).3 (7.). (.3). (.).9 (.9). (.93) CLOSED-LOOP GAIN db. OUTLINE DIMENSIONS Dimensions shown in inches and (mm) PHASE GAIN 3..7 (.).97 (3.) PIN.9 (.). (.) SEATING PLANE.9 (.).9 (.) -Lead Plastic SOIC (SO-). (.). (.). (.7).3 (.3)..9 (.9) (.7).3 (.3) BSC.9 (.).7 (.9) V S =.9 (.).99 (.). (.7). (.) Figure. Closed-Loop Gain and Phase vs. Frequency, Circuit of Figure 3 9 % V mv ns Figure. Pulse Response of the Circuit of Figure 3 with V S = V PHASE SHIFT Degrees PRINTED IN U.S.A. C9b 9/9