Finale Eksamen Kopiereg voorbehou. Final Examination Copyright reserved. Analoogelektronika ENE Junie 2006

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1 Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Department of Electrical, Electronic and Computer Engineering Finale Eksamen Kopiereg voorbehou Analoogelektronika ENE Junie 2006 Final Examination Copyright reserved Analogue Electronics ENE June 2006 Eksameninligting: Examination information: Maksimum punte: Maximum marks: 100 Duur van vraestel: Duration of paper: 180 minute 180 minutes Volpunte: Full marks: 100 Oopboek / toeboek: Oop (Enige materiaal) Open / closed book: Open (Any material) Eksamineringsbeplanning: n Addisionele 10 minute sal aan die begin van die eksaminering beskikbaar gestel word. Gedurende hierdie tydperk mag kandidate nie op die antwoordstelle skryf nie. Test planning: An additional 10 minutes will be availed at the start of the test. During this period, candidates may not make any markings on the answer scripts. Enige toestel met n kommunikasiepoort (van enige aard) word nie toegelaat nie. Any device with a communication port (of whatsoever kind) may not be used. Totale aantal bladsye (hierdie blad ingesluit): Total number of pages (including this page): Die eksamenregulasies van die Universiteit van Pretoria geld. The test & examination regulations of the University of Pretoria apply. BELANGRIK- IMPORTANT 2. Vrae moet in onuitwisbare ink beantwoord word. Geen antwoorde wat in potlood geskryf is sal gemerk word nie. Questions must be answered in indelible ink. Answers in pencil will not be marked. 3. Beantwoord al die vrae en skryf u antwoorde in u Antwoordboek neer. Geen vrae mag op die vraestel beantwoord word nie. Answer all the questions and write the answers in the supplied Answer Book. No questions are to be answered on the Question Paper. 4. Toon alle berekeninge waar van toepassing. Geen punte sal toegeken word vir korrekte antwoorde sonder berekeninge om dit te staaf nie. Show all calculations where applicable. No marks will be given for correct answers without calculations/reasoning to support them. 5. Gebruik duidelik geregverdigde & kundige Ingenieursbenaderings (en/of aannames) waar/indien van toepassing. Use clearly justified & educated Engineering approximations (and/or stated assumptions) where/as appropriate. 6. Datavelle: Vir karakteristieke waar beide tipiese, maksimum en (moontlik) minimum waardes gespesifiseer word, gebruik die tipiese waardes. (tensy anders in vraag gespesifiseer) Datasheets: For characteristics where the typical, maximum and (possibly) minimum values are specified, make use of the typical value (unless/otherwise specified in the question). Dosent: Lecturer: Mr Saurabh Sinha Eksterne Eksaminator: External examiner: Prof. M. du Plessis Vertaler (Engels Afrikaans) Translator (English Afrikaans): Jannes Venter

2 STUDY THEME 1: INTRODUCTION TO AMPLIFIER CIRCUITS QUESTION 1 [8] 1.1 [4] A 14-bit ADC with V FS = 5.12 V has an output code of What is the possible range of input voltages? 1.2 [4] Draw the output voltage waveform for the circuit shown below. Given: R 1 = 2 kω, R 2 = 10 kω and R 3 = 4.7 kω. Assume the operational amplifier is ideal, and the diode has a turn-on voltage of V f = 0.7 V. R 2 v s D 1 +1 V VCC v s R OUT 6 D 2 v o R 3-1 V T t STUDY THEMES 2 & 3 (9): BJT & FET AMPLIFIERS (FREQUENCY RESPONSE) QUESTION 2 [30] The FET used in the problem is the Q2N7000 and the BJT is the Q2N2222 (datasheets of each device is provided). The Early effect may be neglected. V DD = 10 V VCC_BAR R 1A R D R B R C C C C OUT r out vvcc O C IN r in R S1 R E R L R 2A v s 2.1 [20] Using the schematic above, design (provide values for all components) to achieve a small signal input impedance of 50 Ω, a small signal output impedance of 50 Ω, and a mid-band gain of 34 db. Assume that R S1 = 50 Ω, R L = 4 Ω. The low frequency cut-off of the system should be about 100 Hz. Use standard 5 % resistors, and commonly available capacitors (datasheets provided). 2.2 [6] Approximate the Bode magnitude plot for the design. 2.3 [4] Determine the dc power dissipated by each transistor. AFRIKAANS AGTER-OP Page 1

3 STUDY THEME 4: DIFFERENTIAL AMPLIFIERS & BJT AMPLIFIERS QUESTION 3 [13] 3.1 [6] Design the amplifier below to have a small-signal output impedance, R OUT = 1 kω, and differential gain, A dm = 200. The datasheets for the transistors are provided (Q 1/2 is Q2N2222 and Q 3 is Q2N5416 (datasheets provided)). V CC = 9 V VCC_BAR R C R C Q 3 VCC v 1 vvcc 2 VCC v O Q 1 Q 2 R I 1 VCC_BAR V EE = -9 V 3.2 For your design above, determine the: [1] differential-mode voltage gain and input resistance, [0.5] output resistance, [0.5] common-mode input resistance, and [1] CMRR. 3.3 [4] Design a current source (determine the value of R) to provide an output current of I O = 1 ma using the topology shown below (V CC = V EE = 9 V) (Q 1 is Q2N2222 (datasheet provided)) VCC_BAR V R I O VCC_BAR V EE STUDY THEME 5: AMPLIFIER FREQUENCY RESPONSE QUESTION 4 [17] For the amplifier shown on the next page, determine the: 4.1 [8] mid-band gain, 4.2 [2] low frequency cut-off, f L, 4.3 [4] high frequency cut-off, f H, and 4.4 [3] gain-bandwidth product, GBWP. AFRIKAANS AGTER-OP Page 2

4 V VCC_BAR DD Components List VCC v I R S1 C 1 R 2 R 1 R S2 R C C 2 vvcc o R 3 0 V DD = 10 V R 1 = 100 kω R 2 = 300 kω R C = 43 kω R S2 = 3 kω R 6 = 10 kω R 3 = 100 kω R S1 = 100 Ω C 1 = 1 μf C 2 = 0.1 μf C 3 = 2.2 μf R 6 0 C 3 Assume that the transistor is the J2N5457 (datasheet provided). STUDY THEME 6: FEEDBACK QUESTION 5 [21] VCC_BAR V Components List Operational amplifier VCC v I R S OUT Load i OUT 6 Q 1 V CC = 5 V R F = 10 Ω R S = 1 kω (Q 1 is Q2N2222 (datasheet provided)) r in = 50 kω r out = 1 kω A v = 500 R F 5.1 Determine the following characteristics of the feedback amplifier shown: [5] An expression and values for the open-loop gain, A g with the loading by the feedback circuit included [3] An expression and value for the feedback factor, β [3] The closed-loop gain of the amplifier, A fb [3] The closed-loop input impedance, R if of the amplifier [3] The closed-loop output impedance, R of of the amplifier. 5.2 [4] Estimate the maximum load capacitance, C L that can be connected to the output of the voltage follower (below) if the phase margin, Φ M of the amplifier is to be 60. v S OUT 6 vvcc OUT C L Operational amplifier r in = 100 kω r out = 50 Ω A v = 80 db f t = 1.5 MHz AFRIKAANS AGTER-OP Page 3

5 STUDY THEME 7: OUTPUT STAGES AND POWER AMPLIFIERS QUESTION 6 [5] Given: V SS = V DD = 10 V and V BB = 2.2 V. Assume M n and M p are matched. What is the quiescent current in the class AB stage if K p = K n = 1200 µa/v 2 and V TN = V TP = 0.75 V? VCC_BAR V DD V BB M n vvcc OUT M p VCC_BAR V SS QUESTION 7 [6] A BJT is specified to have T j-max = 150 ºC and to be capable of dissipating maximum power as follows: 40 W at T case = 25 ºC 2 W at T air/ambient = 25 ºC Above 25 ºC, the maximum power dissipation is to be derated linearly with Θ device-case = 4 ºC/W, and Θ device-air = 62.5 ºC/W. Find the following: 7.1 [3] The maximum power that can be dissipated safely by this transistor when operated in free air at T air/ambient = 50 ºC. 7.2 [3] The maximum power that can be dissipated safely by this transistor when operated at an ambient temperature of 50 ºC, but with a heat sink for which Θ case-sink = 0.5 ºC/W, and Θ sink-air = 4 ºC/W. In this case, find the temperature of the case and of the heat sink. AFRIKAANS AGTER-OP Page 4

6 For the first design iteration, it would be acceptable to use information provided in the Quick Reference Data. AFRIKAANS AGTER-OP Page 5

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10 2N7000/7002/NDS7002A Page 9

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13 Assume f t = 300 MHz Page 12

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UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS

VAN/SURNAME: UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS VOORNAME/FIRST NAMES: WTW 162 DYNAMICAL PROCESSES EKSAMEN