Multi-Process Systems: Memory (1) The Basic Memory Hierarchy. Contemporary Memory Hierarchy & Dynamic Loading. (Executable) Secondary Primary

Transcription

1 Multi- Systems: (1) What we will learn A detailed description of various ways of organizing memory Discuss various memory-management techniques, including paging and segmentation To provide a description hardware support Address augmentation: Swapping Address augmentation: Virtual Background Demand Paging Page Replacement Allocation of Frames Thrashing -Mapped Files Allocating Kernel Other Considerations Operating-System Examples 2 The Basic Hierarchy CPU Registers More Frequently Used Information Primary (Execu ) e.g. RAM Less Frequently Used Information Secondary e.g. Disk or Tape Larger storage Contemporary Hierarchy & Dynamic Loading Secondary Primary (Execu) CPU Registers L1 Cache L2 Cache Main Rotating Magnetic Optical Sequentially Accessed 3 Faster access 4

2 Exploiting the Hierarchy Upward moves are (usually) copy operations Require in upper memory Image exists in both higher & lower memories Updates are first applied to upper memory Downward move is (usually) destructive Destroy image in upper memory Update image in lower memory The cache principle Place frequently-used info high, infrequently-used info low in the hierarchy Reconfigure as process changes phases 5 6 The Manager (External view) exec() shmalloc() sbrk() getrlimit() File Mgr UNIX Device Mgr Mgr Mgr Application Program Hardware File Mgr Device Mgr VirtualAlloc() VMQuery() VirtualLock() VirtualFree() Zero() Mgr Mgr Windows The Manager (Abstract / logical view) Translation system creates an, but its are virtual instead of physical A virtual, x: Is mapped to physical y = B t (x) if x is loaded at physical y Is mapped to! if x is not loaded B t : Virtual Address " Physical Address # {!} The map, B t, changes as the process executes -- it is time varying 7 8

3 The Manager (Abstract / logical view) virtual x B t! y = B t (x) Absolute Program Address Space The Manager (Internal view) Address Space User Address Space Primary 3GB 4GB Supervisor Address Space 9 1 CPU CPU chip Virtual es from CPU to MMU Physical es on bus, in memory The Manager (Hardware view) MMU Disk controller Program uses logical or virtual es Addresses local to the process Hardware translates virtual to physical Translation done by the Management Unit Usually on the same chip as the CPU Only physical es leave the CPU/MMU chip Physical memory indexed by physical es Manager Requirements Minimize execu memory access time Maximize execu memory size Execu memory must be cost-effective Today s memory manager: Allocates primary memory to processes Maps process to primary memory Minimizes access time using cost-effective memory configuration May use static or dynamic techniques 11 12

4 and multiprogramming needs at least two things for multiprogramming Allocation/Relocation strategies Protection The cannot be certain where a program will be loaded in memory s and procedures can t use absolute locations in memory Several ways to guarantee this The must keep processes memory separate Protect a process from other processes reading or modifying its own memory Protect a process from modifying its own memory in undesirable ways (such as writing to program code) 13 Augmenting organization () HW support The big picture Contiguous Swappig Virtual Non contiguous Limit & relocation Page request Page replacement Dedicated Paging Dynamic Table based Page Frame TLB Paging & Segment 14 Allocation/relocation strategies -Partition used only in batch systems -Partition used everywhere (except in virtual memory) Swapping systems Popularized in timesharing Relies on dynamic relocation Now dated Dynamic Loading (Virtual ) Exploit the memory hierarchy Paging -- mainstream in contemporary systems -- the future Protection The hw and operating system must co-operate to ensure that different processes do not modify each other s memory The hw provides special that can be read in user mode, but only modified by instructions in supervisor mode Simple solution: the physical memory is divided between processes in contiguous chunks by the and the boundsare stored in special the hardware checks every program access to ensure it is within bounds 15 16

5 Protection Virtual memory allows protection without the requirement that pages be pre-allocated in contiguous chunks Physical pages are allocated based on program needs and physical pages belonging to different processes may be adjacent efficient use of memory Each page has certain read/write properties for user/ kernel that is checked on every access a program s execu can not be modified part of kernel data cannot be modified/read by user page s can be modified by kernel and read by user Augmenting organization () HW support The big picture Non contiguous Contiguous Swappig Virtual Limit & relocation Page request Page replacement Dedicated 17 Paging Dynamic Table based Page Frame TLB Paging & Segment 18 Contiguous Allocation Main memory usually into two partitions: Resident operating system, usually held in low memory with interrupt vector User processes then held in high memory Assumes a single hunk of memory per process xffff partition HW protection: Base and limit Special CPU : base & limit Access to the limited to system mode Registers contain Base: start of the process s memory partition Limit: length of the process s memory partition Address generation y = B t (x) Physical y: location in actual memory Logical x: location from the process s point of view B t (x) = base + logical! : Logical larger than limit => error xffff 19 partition x2 Limit Base x9 Logical : x124 Physical : x124+x9 = xa24 2

6 HW protection: Runtime Bound Checking CPU Relative Address Relocation Register Limit Register < $ Interrupt Bound checking is inexpensive to add Provides excellent memory protection + MAR xffff partition Contiguous Allocation (Cont.) Multiple-partition Hole block of available memory; holes of various size are scattered throughout memory When a process arrives, it is allocated memory from a hole large enough to accommodate it Operating system maintains information about: a) allocated partitions b) free partitions (hole) process 5 process 8 process 2 21 process 5 process 2 process 5 process 9 process 2 process 5 process 9 process 1 process 2 22 (size) Partition mechanism Divide memory into fixed s maximum number of processes maximum process size Assign a process to a when it s free Mechanisms Separate input queues for each partition Single input queue: better ability to optimize CPU usage Partition 4 Partition 3 Partition 2 Partition 1 9K 7K 6K 5K Partition 4 Partition 3 Partition 2 Partition 1 9K 7K 6K 5K 1K 1K 23 Partition Mechanism Operating System Loader adjusts every in every absolute module when Operating System Operating System Operating System External fragmentation Compaction moves program in memory placed in memory 24

7 Partition Mechanism: the cost of moving load R1, x21 3F131 Program loaded at x1 3F161 Program loaded at x4 Must run loader over program again! Consider dynamic techniques Dynamic Allocation Could use dynamically allocated memory wants to change the size of its Smaller % Creates an external fragment Larger % May have to move/relocate the program Needs to keep track of memory usage Allocate holes (a free memory segment) in memory according to Best- /Worst- / First- /Next-fit Needs to keep track of memory usage Tracking memory usage: bitmaps Keep track of free / allocated memory regions with a bitmap One bit in map corresponds to a fixed-size region of memory Bitmap is a constant size for a given amount of memory regardless of how much is allocated at a particular time Chunk size determines efficiency At 1 bit per 4KB chunk, we need just 256 bits (32 bytes) per MB of memory For smaller chunks, we need more memory for the bitmap Can be difficult to find large contiguous free areas in bitmap A B C D Tracking memory usage: linked lists Keep track of free / allocated memory regions with a linked list Each entry in the list corresponds to a contiguous region of memory Entry can indicate either allocated or free (and, optionally, owning process) May have separate lists for free and allocated areas Efficient if chunks are large -size representation for each region More regions => more needed for free lists A B C D regions Bitmap regions A B C 17 9 D

8 Allocating memory Search through region list to find a large enough Suppose there are several choices: which one to use? First fit: the first sui hole on the list Next fit: the first sui after the previously allocated hole Best fit: the smallest hole that is larger than the desired region (wastes least?) Worst fit: the largest available hole (leaves largest fragment) Option: maintain separate queues for different-size holes Allocate 2 blocks first fit Allocate 13 blocks best fit Allocate 12 blocks next fit Allocate 15 blocks worst fit Freeing memory Allocation structures must be updated when memory is freed Easy with bitmaps: just set the appropriate bits in the bitmap Linked lists: modify adjacent elements as needed Merge adjacent free regions into a single region May involve merging two regions with the just-freed area A X B A X X X B A A B B 3 Buddy Goal: make it easy to merge regions together after Use multiple bitmaps Track blocks of size 2 d for values of d between (say) 12 and 17 Each bitmap tracks free blocks in the same region of different sizes Keep a free list for each block size as well Store one bit per two blocks Blocks paired with buddy : buddies differ in block number only in their lowest-order bit Bit == : both buddies free or both buddies allocated Bit == 1: exactly one of the buddies is allocated, and the other is free Fragmentation External Fragmentation total memory exists to satisfy a request, but it is not contiguous Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block Compaction is possible only if relocation is dynamic, and is done at execution time I/O problem Latch job in memory while it is involved in I/O Do I/O only into buffers 31 32

9 Augmenting organization () HW support The big picture Non contiguous Contiguous Swappig Virtual Limit & relocation Page request Page replacement Dedicated Paging Dynamic Table based Page Frame TLB Paging & Segment Paging Logical of a process can be non contiguous; process is allocated physical memory whenever the latter is available Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8,192 bytes) Divide logical memory into blocks of same size called pages Keep track of all free frames To run a program of size n pages, need to find n free frames and load program y = B t (x) : Set up a page to translate logical to physical es Internal fragmentation Paging and page s Virtual es mapped to physical es All es in the same virtual page are in the same physical page Page entry (PTE) contains translation for a single page Table translates virtual page number to physical page number Not all virtual memory has a physical page Not every physical page need be used Example: 64 KB virtual memory 32 KB physical memory 6 64K 56 6K K 48 52K K K K 32 36K K K 2 24K K 12 16K 8 12K - 4 8K 4 4K 7 Virtual 28 32K 24 28K 2 24K 16 2K 12 16K 8 12K 4 8K 4K Physical memory What s in a page entry? Each entry in the page contains Valid bit: set if this logical page number has a corresponding physical frame in memory If not valid, remainder of PTE is irrelevant Page frame number: page in physical memory Referenced (Used) bit: set if data on the page has been accessed Dirty (modified) bit :set if data on the page has been modified Protection information Protection Dirty bit D R V Referenced or Used bit Page frame number Valid bit 35 36

10 Paging model A page is a fixed size, 2 h, block of virtual es A page frame is a fixed size, 2 h, block of physical memory (the same size as a page) When a virtual, x, in page i is referenced by the CPU If page i is loaded at page frame j, the virtual is relocated to page frame j If page is not loaded, the interrupts the process and loads the page into a page frame Paging model : Addresses Suppose there are G= 2 g &2 h =2 g+h virtual es H= 2 j &2 h =2 j+h physical es assigned to a process Each page/page frame is 2 h es There are 2 g pages in the virtual 2 j page frames are allocated to the process Rather than map individual es B t maps the 2 g pages to the 2 j page frames That is, page_frame j = B t (page i ) Address k in page i corresponds to k in page_frame j Example How many entries would there be in a process page in a system with 32-bit es and a 1K page size? 1K= 124=2 1 =2 h, h=1 G=2 32 N= 2 g = G/2 h = 2 32 / 2 1 = 2 22 g=22 N=2 12!2 1 = 496K or over 4 million. Paging model: Address Translation Let N = {d, d 1, d n-1 } be the pages Let M = {b, b 1,, b m-1 } be page frames Virtual i, satisfies 'i<g= 2 g+h Physical k = U2 h +V ('V<G= 2 h ) U is page frame number V is the line number within the page B t :[:G-1] " <U, V> # {!} Since every page is size c=2 h page number = U = (i/2 h ) = (i/c) line number = V = i mod c 4

11 // // // TranslateUserToSystem // //!Translate a user (in the process referenced by pcb) //!into an (physical). This works for simple one-level //!page s, but will have to be modified for two-level page //!s. // // uint32 TranslateUserToSystem (PCB *pcb, uint32 addr) { int! page = addr / MEMORY_PAGE_SIZE; int offset = addr % MEMORY_PAGE_SIZE; } Address Translation with Paging if (page > pcb->npages) { return (); } return ((pcb->page[page] & MEMORY_PTE_MASK) + offset); U = (i/2 h ) V = i mod (i/2 h ) Example: translation Split from CPU into two pieces Page # (p) Page offset (d) Page number Index into page Page contains base of page in physical memory Page offset Added to base to get actual physical memory Page size = 2 h bytes Example: 4 KB (=496 byte) pages 32 bit logical es 2 h = 496 h = 12 g=32-12 = 2 bits p 12 bits d 32 bit logical 41 Operating Systems and 42Distributed Systems Address translation architecture page number page offset (=line) Page frame number Page frame number CPU p d 1 p-1 p p+1. f page f d physical. memory f-1 f f+1 f+2