PHYSICS LAB #5 Basic Digital Circuits and Flip-Flops

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1 PHYSICS LAB #5 Basic Digital Circuits and Flip-Flops Objectives: Construct a two-bit binary decoder. Study the multiplexers (MUX) and demultiplexers (DEMUX) Construct the basic SR flip-flop. Study the D-latch and J-K latches. Explore the applications of using latches, decoders, MUX and DEMUX Introduction: In this lab we explore some relatively simple digital circuits, many of which are available in a single chip. We consider flip-flops, which are the basic building blocks of all memory systems and study the encoders/decoders, multiplexers (data selectors) and demultiplexers (data distributors). We will explore some applications of flip-flops, latches and MUX/DEMUX. Decoders and Encoders: A decoder circuit takes information presented in one form and decodes or converts into another form. There are many different kinds of decoders. The most common examples are decoder that converts the binary number into BCD (binary coded decimal) number (IC chip 7484) and BCD numbers into binary number (IC chip 7485). Another commonly found decoder circuit is a BCD to seven segment decoder used in driving the signals for sevensegment LED display. An encoder is the opposite of a decoder. Flip-Flops and Latches: A flip-flop is essentially any circuit with two output terminals and two stable voltage states (one higher than the other) for each terminal. A flip-flop is a basic binary storage element, which holds or latches binary information indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch the states. These devices are very useful in detecting occurrence of an event and counting the number of events occurred. There is no general agreement on which names should be used for these devices. Some refer to them as flip-flops and other call them latches. Multiplexers and Demultiplexers: A multiplexer or data selector is the electrical analog of a rotary multi-position mechanical switch. It can select any of several input lines and direct that input line to a single output terminal. There are 2 n X input MUXes and they have n input selection lines or address lines. For example an 8 input (n = 3) MUX has 3 input selection lines and can select any of one of the 8 input (000 selects line 0, 00 selects line... selects line 7) lines and connect it to the output line depending on the address selected by the address lines Inverse of the multiplexer is the demultiplexer or data distributor. It is also like a rotary mechanical switch except the information flow is from the single input to one of 2 n output lines selected by n address lines.

2 Experiments: 5-. Two-bit Binary Decoder: Construct the two-bit binary decoder using four NAND gates and two NOT gates. Connect the outputs D0, D, D2 and D3 to logic indicators 8, 7, 6 and 5, respectively. Fill in the truth table for various input combinations. A B 2X4 Decoder D0 D D2 D3 A B D0 D D2 D3 Fig. 5- Two-bit Binary Decoder 5-2. An Eight Input Multiplexer (MUX): Truth Table Inputs Outputs A B D 3 D 2 D D The 74LS5 MUX has eight data input lines and three address lines to select the desired data input (see Fig. 5-2). There is also an enable ( E) input and only when this is connected to ground (LOW) the selected input is connected to the output line. Connect the circuit as shown in Fig. 5-2 (with pin numbers). Connect the output Q to one of the LED indicators and E to ground so that the selected input is always passed on to the output line. Select an address by setting address lines (000 to ). Connect the Hz TTL pulses to all the input lines in succession and see which one is passed on to the output line (when you connect the TTL pulses to the line selected the LED should blink at Hz). Fill the following truth table. 2

3 +5V 6 D0 D D2 8X D3 D4 MUX D5 D6 D7 A2 A A0 Output Inputs D0 D D2 D3 D4 D5 D6 D7 E Q Q 74LS5 A0 A A2 GND Outputs Address lines Fig. 5-2 Eight Input MUX Truth table A 2 A A 0 D i The Simple RS Flip-Flop with Two NAND Gates: Construct an RS flip-flop from two NAND gates of the 7400 IC as shown in Fig Connect the outputs Q and Q to two LED indicators. By applying HIGH and LOW logical levels to S and R inputs, verify the truth table. In the RS flip-flop constructed from NAND gates, a change of state effected by bringing LOW the input of the NAND gate which had both inputs HIGH. Hence the bars on the inputs R and S. S 2 3 Q R Q Fig. 5-3 RS Flip-Flop 3

4 Truth Table Inputs Gate # Gate #2 Inputs Output Inputs Output S R 2 Q 4 5 Q Does a HIGH to both S and R change the outputs Q and Q from their previous levels? Explain your answer. What happens when both S and R are LOW? Is it allowed? Why not? Explain The clocked Data Latch or D-Flip-Flop: The output of the RS flip-flop responds immediately to input changes, except for a small delay (gate delay) caused by the time taken for the current to flow through the transistor switches. These uncontrolled delays can play havoc in complex digital circuits. Having a system clock solves this problem. In clocked digital circuits the changes occur, throughout the system, in unison only when the clock allows it to. The output of the clocked flip-flops respond to input only when the clock pulse (CP) input changes. The 7474 (Fig. 5-4) is a dual D-latch that passes data from input (D) when the CP changes LOW to HIGH. For this reason it is called "positive-edge triggered" or "rising-edge triggered" latch. The 7474 IC is also provided with switches for immediate response also. These are labeled as Set and Reset. Again the inversion bars on Set and Reset indicate that these inputs respond on LOW signals. You need to construct a circuit to produce a clock pulses. This can be done by using push button (PB) switches available on the design station. Construct the circuit shown in Fig Check that the push buttons produce the desired pulses using an LED indicator lights. Save this circuit. 4

5 Fig 5-4 Now construct the circuit with one of the D-latches from 7474 IC as shown below in Fig Connect the outputs Q and Q to two LED indicators. Verify that the input does not appear on the output until CP goes HIGH. Also check that Q goes HIGH immediately, if you make Set LOW and Q goes LOW immediately, if you make Reset LOW. Fig. 5-5 The 7474 Type D-Latch Draw a timing diagram for the operation of the D-latch. 5

6 5-5. The JK Flip-Flop: The simple RS flip-flop constructed from NAND gates cannot handle both inputs simultaneously LOW and it is not allowed. The JK flip-flop overcomes this problem. The JK flip-flop has two inputs (labeled J and K) that affect the outputs (Q and its complementary Q ) synchronously with the clock inputs. Some JK flip-flops have preset and clear inputs that make the output go HIGH or LOW immediately. These are also called direct set and direct clear inputs. The 74LS07 IC is dual JK latch and has direct clear input. This JK latch is "negativeedge" or "falling-edge" triggered. This is indicated by a small open circle at the CP input. Thus it is a level-sensitive circuit. Fig LS07 JK Flip-Flop Connect the output of one of the JK-FFs to an LED indicator and use the CP from the circuit of Fig For various inputs of JK fill the truth table (function table) shown below. Note that Qn is the state of the output (HIGH or LOW) any time and Q n+ is the state of the output after the change in CP. J K Qn Qn

7 Summarize your observations as following: The output changes when CP goes When both J = K = the out put When J= and K=0 the output When K = and J = 0 the output When J = K = 0 the output 5-6. Applications: We can think of using the standard gates, encoders/decoders, multiplexers/demultiplexers etc., in several interesting applications. Here are some examples Gating Pulses: Any two (or more) input gate can be used to control or gate pulses. The pulses go into one input (called the clock input) and the control that turn the pulses ON or OFF goes into the other input (called the control input). Connect one AND gate input to the Hz TTL clock output and the other AND gate input to a data switch (you can create it by plugging the lead into +5V or ground manually). Connect the output of the AND gate to LED indicator #8 and the clock to LED indicator #. Sketch the output for the control input shown below. Describe your observations. Can you think of an application of this circuit? 7

8 5-6.2 Prime Number Detector Circuit: Here is a logic circuit (Fig. 5-7) using basic gates that takes in 3-bit binary number xyz and produces a single output F that is true if the input represents a prime number between 0 and 7. Connect and check the circuit. Report your observation in a table that includes binary number that you put in, its equivalent decimal number and the output (Yes or No). x y z F Fig. 5-7 Prime Number Detector Circuit Starting from truth table show that F = x y + z. Use the back page or a separate sheet Full Adder: All modern digital computers are essentially very-high-speed adding machines and memory circuits designed to handle numbers in binary form. We need to add two binary numbers consisting of several binary digits. This requires, often, addition of two digits and a carry in from a previous stage (a total of three binary digits) and produce a sum and a carry over digit. We can accomplish this by a digital circuit that is usually called a full adder. A half adder adds only two digits and cannot take in a carry in. It is only good for adding two least significant digits of two binary. Construct the full adder shown in Fig. 5-8 and verify its truth table. Fig. 5-8 Full-adder Circuit Work out the Boolean expressions for Cn and Sn from the above logic circuit. Use the back page or a separate sheet. 8

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