Signal Integrity in Digital Systems

Transcription

1 ECE 570 Session 11 Part 2 IC 752-E Computer Aided Engineering for Integrated Circuits Signal Integrity in Digital Systems Objective: Basics signal integrity concepts Outline: 1. Circuit attributes for signal integrity 2. Electrical systems 3. Interconnect modeling 4. Modeling criteria 0

2 1. Circuits attributes for signal integrity LOGIC SWING, RISE AND FALL TIMES, CYCLE TIME V V H 01. V LS V LS F HG I K J V V V H L 2 T c V L 01. V LS t t r t f 1

3 Logic swing V = V V = LS H L R S T 5volts 33. volts 08. volts U V W CMOS BJT Rise time - t r, Fall time t f t r = t = f R S T ps CMOS ps BJT Cycle time T c 2

4 Estimation of Highest Frequency of Interest Using Rise Time Fundamental frequency ν o = 1 Tc Taking 3-rd harmonic as highest frequency to be transmitted 3 f max = A simplified relation the rise time and cycle time yields Example: t p r = 100 sec f T c max T c = 10 t T c r. = fmax = = 3 GHz

5 Characterization of logic circuits (terminal properties) Static: transfer curve (transfer characteristic) V DD =const V IN V OUT V SS =const The transfer curve is used to determine logic swing switching threshold noise tolerances noise margins noise immunities 4

6 A prototypical transfer curve (steady state response) NM L *- UNITY GAIN Points (slope = -1) V OUT NM H Switching Threshold Voltage V T NT L NT H V IN L V IN H V IN NT H L - noise tolerance (sensitivity); NM H L - noise margin Noise immunity (NI): NI H L = NT V H L LS 5

7 Transient response: Dynamic characterization V IN and V OUT are transitioning between "high" and "low " levels V DD =const V IN V OUT V SS =const yielding: a) gate delay (internal delay) b) dynamic noise tolerance 6

8 a) Definition of gate delay, t D, (aka internal delay) V IN V L IN + 1 V 2 IN LS t D1 t D2 t V OUT V L OUT + 1 V 2 OUT LS 1 t = t + t D b g 2 D1 D 2 t 7

9 b) Dynamic noise tolerance (DNT) PA Forbidden Area NT L NM L Area of safe operation PW The DNT curves are generated using circuit simulation with perturbing pulses A[V] PA PW 0 t r PW-t r t added to the input signal. The DNT are determined via receiver characterization or circuit simulation. 8

10 Dynamic characterization of logic circuits Dynamic noise tolerance for receivers Driving capability for drivers determined through study of driver-line interaction via circuit simulation characterization Driver power (current ) demand (needed for estimation of switching perturbations) - determined via circuit simulation characterization 9

11 1. Signal distribution system Problems: 2. Electrical Systems signal delay signal distortion via coupling noise switching noise reflections losses (causing attenuation and dispersion) 2. Power and ground distribution system Problems: DC voltage drop switching noise 3. Externally coupled systems: E-M Interference (EMI) Electro-static discharge (ESD) 10

12 Signal interconnections 3. Interconnect Modeling finite impedance (40-70 Ω ) low currents components traces on-chip and bonds (WB, TAB, FC) conductors on chip carriers and connections (pins, SMT, balls) PWB conductors connectors Power and ground connections very low impedance ( mω, µ Ω ) - lower than better higher currents ( ma, A) components traces on-chip and bonds conducting plates in packages and boards 11

13 Modeling: Coupling: Remarks concerning on-chip interconnections capacitive inductive propagation modes Technological trends - effects of scaling increased capacitive coupling increased importance of process variations decreased noise immunity decreased reliability (electromigration), yield (contamination effects) 12

14 Qualitative discussion of interconnect behavior General comments on inductive effects I(t) Loop A Loop B Magnetic field strength (and the flux) is proportional to loop current. A fraction of the magnetic flux from the loop A encompasses the loop B. Voltage induced in the loop B is proportional to the rate of change of flux in the loop A. Ground planes keep the loops small and local thus reducing inductive coupling. Inductive coupling reaches farther (encompasses more conductors) than capacitive coupling, which typically is more localized and decays rapidly with the distance. 13

15 Effect of backplane Removed ground plane Ground (backplane) included E ( t ) E ( t ) H ( t ) H ( t ) The resistive losses in the substrate are approximated by tan δ 1 b g = ωε rε oρ Depending on frequency and resistivity the substrate may behave as a conductor or a dielectric and may determine various signal propagation modes yielding various velocities of signal propagation. 14

16 hresults of approximate analysis Idealized structure Graphical representation of results b 1 b 2 x Signal line ( ρ = 0) Oxide ( ρ = ) Silicon ( ρ - finite) 2 1 y f [ MHz] Skin- Effect Mode Quasi- TEM Mode 0 10 Slow-wave Mode Ground plane ( ρ = 0) [ Ω ] ρ2 cm Example for: b1 m, b2 (Grabinski, 1991). = 1µ = 400µ m 15

17 Capacitive coupling is important Example of prototypical results for fixed distance to the ground ( 2µm ) 5 C[ pf / cm] C t C G C C 0 Conductor width [cm] 5 C G - capacitance to the ground, C c - coupling capacitance (to the neighbor) C t - total capacitance 16

18 Trends Increasing number of layers is needed due to chip complexity. Lines are longer and require higher aspect ratio to cope with space and attenuation restriction - consequently they exhibit more crosstalk. Processing variations are more important because lines are very tight and narrower. Hierarchical wiring is needed: RC models for lower levels, TL for higher levels. Skin effect might be important on higher level interconnects Skin depth: δ 2 = ωρµ ; σ 2µ m for copper at 1 GHz. 17

19 Example of effects caused by interconnect geometry scaling by a factor of 2 and a reduction of supply voltage from 2.5 [V] to 1.8 [V]. Geometry Base technology: W = 09. µ m, S = 09. µ m, T = 09. µ m, k c = 053. Scaled technology: W = 045. µ m, S = 045. µ m, T = 073. µ m, k c = Typical circuit noise immunity: mb g r b g mb g r b g Base technology: mv / 2. 5 V yields % of V DD Scaled technology: mv / 18. V yields % of V DD. Typical relative signal coupled noise mb g r b g mb g r b g Base technology: mv / 2. 5 V yields % of V DD Scaled technology: mv / 18. V yields % of V DD. 18

20 4. Modeling Criteria for Signal Interconnections (based on single line analysis) Schematic of a line 0 D x + V A - + VB - Basic relation used in derivation: π λ = v 2 ω Frequency domain criteria are based on comparison of line length to minimum signal wavelength as determined by the higher frequency signal to be transmitted through the interconnecting line. 19

21 Simplified criteria tr 100 td tr 4 < < 100 td tr 4 t D - ideal wire - lumped RC - transmission line Alternative criteria (rule of thumb used by some designers): If t r > 25. t D use lumped model If t r > 25. t D use transmission line model A useful relation to estimate time of flight: td = D c = Dτ ; τ 333. εr ps/ cm. 20

22 Exercise Determine model required for the interconnect of geometry given below 1 Dimensions are given in mils 0.4 ε r1 =1 2 ε r2 =9 (Al 2 O 3 ) Assume rise time t r = 100 ps and consider two cases: a) interconnect on chip carrier where D= 60 mls i b) interconnect on a board where D cm =