Features. Applications. Truth Table. LED Output (V O )

Transcription

1 ACPL-M7T and ACPL-M72T High Speed, Low Power Digital Optocouplers with R 2 Coupler Isolation and AEC-Q Grade Qualification Data Sheet Description The Avago ACPL-M7T and ACPL-M72T are high temperature, digital CMOS optocouplers in SOIC- packages. Suitable for hybrid and electric vehicle applications, the optocouplers use the latest CMOS IC technology to achieve outstanding performance and very low power consumption. All devices are AEC-Q compliant and operate over the C to 2 C temperature range. The ACPL-M7T uses a high speed LED, and the ACPL-M72T uses a low current LED for lower power dissipation. The high speed ACPL-M7T featuring a ns maximum propagation delay (I F = ma). The ACPL-M72T optocoupler features very low power. With a low ma LED drive current, ACPL-M72T typical propagation delay is ns. Each digital optocoupler has a CMOS detector IC, an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. Avago R 2 Coupler isolation products provide the reinforced insulation and reliability needed for critical in automotive and high temperature industrial applications Functional Block Diagram Features V CMOS compatible Common-Mode Rejection V CM =V: Wide automotive temperature range: C to 2 C Low propagation delay : High Speed ACPL-M7T: I F = ma (Typical) Low Power ACPL-M72T: I F = ma (Typical) Worldwide safety approval: UL 77 recognized, Vrms / min CSA approved IEC/EN/DIN EN 77-- Qualified to AEC-Q Grade test guidelines Applications Automotive CANBus communications interface Automotive isolated high speed gate drivers for IGBTs and Power MOSFETs High temperature digital signal isolation Microcontroller interface Digital isolation for A/D and D/A conversion ACPL-M7T/ACPL-M72T Vdd Anode V o Truth Table Cathode Gnd LED Output (V O ) OFF H ON L Note: A. µf bypass capacitor must be connected between pins and. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Ordering Information Part Number Option (RoHS) Compliant Package Surface Mount Tape & Reel IEC/EN/DIN EN 77-- Quantity ACPL-M7T -E SO- X per tube -E X X per tube -E X X per reel -E X X X per reel ACPL-M72T -E SO- X per tube -E X X per tube -E X X per reel -E X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. For example, the part number ACPL-M7T-E describes a device with a surface mount SOIC- package; delivered in Tape and Reel with parts per reel; and full RoHS compliance. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Dimensions ACPL-M7T / ACPL-M72T (JEDEC MO- Package). ±. (.7 ±.) M7T YWW EE 7. ±.2 (.27 ±.8) A CATHODE V CC V OUT GND. ±.* (.2 ±.). ±. (. ±.2) Extended Datecode for lot tracking 2. ±. (.98 ±.).2 ±.2 (. ±.).2 ±.2 (.8 ±.).27 (.) BSC.7 (.28) MIN 7 MAX. DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS. mm (.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. MAX. LEAD COPLANARITY =.2 (.) 2

3 Land Pattern Recommendation. (.7) 2. (.). (.) 2. (.8) 8.27 (.2). (.2) DIMENSION IN MILLIMETERS (INCHES) Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-2 (latest revision). Note: Non-halide flux should be used. Regulatory Information The ACPL-M7T and ACPL-M72T are approved by the following organizations: UL Approved under UL 77, component recognition program up to V ISO = V RMS. CSA Approved under CSA Component Acceptance Notice #. IEC/EN/DIN EN 77-- IEC 77--: EN 77--: DIN EN 77--:

4 Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(I) > mm Measured from input terminals to output terminals, shortest distance through air. L(I2) > mm Measured from input terminals to output terminals, shortest distance path along body..8 mm Insulation thickness between emitter and detector; also known as distance through insulation. CTI >7 V DIN IEC 2/VDE Part Isolation Group IIIa Material Group (DIN VDE 9) IEC/EN/DIN EN 77-- Insulation Related Characteristics Description Symbol ACPL-M7T/ ACPL-M72T Units Maximum Working Insulation Voltage V IORM 7 V PEAK Input to Output Test Voltage, Method b V IORM x.87 = V PR, % Production Test with t m = sec, Partial Discharge < pc Input to Output Test Voltage, Method a V IORM x. = V PR, Type and Sample Test, t m = sec, Partial Discharge < pc Highest Allowable Overvoltage (Transient Overvoltage, t ini = sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure.) V PR V PEAK V PR 97 V PEAK V IOTM V PEAK Case Temperature T s C Input Current I s, INPUT ma Output Power P s,output mw Insulation Resistance at T S, V IO = V R IO 9 Ω

5 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Condition Storage Temperature T S + C Ambient Operating Temperature [] T A +2 C Supply Voltages V DD. V Output Voltage V O. V DD +. V Average Forward Input Current I F 2. ma Peak Transient Input Current (I F at µs pulse width, <% duty cycle) I F( TRAN) 8 Reverse Input Voltage V r V Input Power Dissipation P I mw Output Power Dissipation P o mw Lead Solder Temperature Solder Reflow Temperature Profile A ma 2 C for sec.,. mm below seating plane See Solder Reflow Temperature Profile Section < µs Pulse Width, pps < µs Pulse Width, <%Duty Cycle Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature T A +2 C Supply Voltages V DD.. V Forward Input Current I F(ON). ma Forward Off State Voltage V F (OFF).8 V Input Threshold Current I TH. ma

6 Electrical Specifications Over recommended temperature (T A = C to +2 C),. V V DD. V. All typical specifications are at T A =+2 C, V DD = +V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig Input Capacitance C IN 9 pf Input Reverse Breakdown Voltage BV R. V I R = µa Logic High Output Voltage V OH V DD -. V I OH = -ma Logic Low Output Voltage V OL. V I OL = ma Logic Low Output Supply Current Logic High Output Supply Current I DDL.9. ma I DDH.9. ma LED Forward Voltage Vf...7 V I F =ma, Ta=2 C.2..8 V I F =ma, Ta= - C ~ 2 C Vf Temperature Coeficient -. mv/ C ACPL-M7T High Speed Mode Switching Specifications Over recommended temperature (T A = C to +2 C),. V V DD. V. All typical specifications are at T A =+2 C, V DD = V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig Note Propagation Delay Time to Logic Low Output [] Propagation Delay Time to t PHL t PLH 2 2 ns ns V in =.V-.V, R in =9Ω+/-%, C in =pf, C L = pf Logic High Output [] Pulse Width Distortion [2] PWD 2 ns Propagation Delay Skew [] t PSK ns Output Rise Time (% 9%) Output Fall Time (9% - %) Common Mode Transient Immunity at Logic High Output [] Common Mode Transient Immunity at Logic High Output [] t R ns t F ns CM H 2 kv/µs V in =V Rin=9Ω +/-%, C in =pf, V cm =V, T A =2 C CM L 2 kv/µs V in =.V-.V, R in =9Ω +/-%, C in =pf, V cm =V, T A =2 C,,,2, 2

7 ACPL-M72T Low Power Mode Switching Specifications Over recommended temperature (- C to +2 C),.V V DD.V. All typical specifications at +2 C and VDD = V Parameter Symbol Min. Typ. Max. Units Test Conditions Fig Note Propagation Delay Time to Logic Low Output [] Propagation Delay Time to t PHL t PLH ns ns I F =ma, C L =pf 7,8, 9,, Logic High Output [] Pulse Width Distortion [2] PWD 2 ns Propagation Delay Skew [] t PSK ns Output Rise Time (% 9%) Output Fall Time (9% - %) Common Mode Transient Immunity at Logic High Output [] Common Mode Transient Immunity at Logic High Output [] t R ns t F ns CM H 2 kv/µs Using Avago LED Driving Circuit, V IN =V, R =Ω+/-%, R 2 =Ω+/-%, V CM =V, T A =2 C CM L 2 kv/µs Using Avago LED Driving Circuit, V IN =.-.V, R =Ω+/-%, R 2 =Ω, V CM =V, T A =2 C,2, Package Characteristics All Typical at T A = 2 C. Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Momentary Withstand Voltage V ISO V rms RH %, t = min., T A = 2 C Input-Output Resistance R I-O Ω V I-O = V dc Input-Output Capacitance C I-O. pf f = MHz, T A = 2 C Notes:. t PHL propagation delay is measured from the % (Vin or If) on the rising edge of the input pulse to.8v on the falling edge of the V O signal. t PLH propagation delay is measured from the % (Vin or If) on the falling edge of the input pulse to the 8% level of the rising edge of the V O signal. 2. PWD is defined as t PHL - t PLH.. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions.. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. 7

8 Performance Plots IF - Forward Current (ma).... Ta = 2 C Vo - Output Voltage (V) V F - Forward Voltage - V Figure. Typical Diode Input Forward Current Characteristic.. 2 I F - Forward Current - ma Figure 2. Typical Output Voltage vs Input Forward Current VOL - Logic Low Output Voltage - V I OL - Logic Low Output Current - ma Figure. Typical Logic Low Output Voltage vs Logic Low Output Current VOH - Logic High Output Voltage - V I OH - Logic High Output Current - ma Figure. Typical Logic High Output Voltage vs Logic High Output Current Tp - Propagation Delay, PWD - Pulse Width Distortion - ns 2 2 T PHL Vin=.V, Rin=9Ω, Cin=pF T PLH PWD Temperature - C Figure. ACPL-M7T (High Speed)Typical Propagation Delay vs Temperature Tp - Propagation Delay, PWD - Pulse Width Distortion - ns T PHL Rin=9Ω, Cin=pF T PLH Ta=2 C PWD I F - Forward Current - ma Figure. ACPL-M7T (High Speed)Typical Propagation Delay vs Forward Current - I F 8

9 Width Distortion - ns 2 2 T PHL I F=mA T PLH PWD Temperature - C Figure 7. ACPL-M72T (V) Typical Propagation Delay vs Temperature Tp - Propagation Delay, PWD - Pulse Width Distortion - ns T PHL T PLH PWD Ta=2 C I F - Forward Current - ma Figure 8. ACPL-M72T (V) Typical Propagation Delay vs Forward Current - I F TP - Propagation Delay - ns I F = ma, V DD =V T PHL T PLH PWD T A - Temperature - C Figure 9. ACPL-M72T (V) Typical Propagation Delay vs Temperature TP - Propagation Delay - ns T A = 2 C, V DD =V T PHL T PLH PWD I F - Forward Current - ma Figure. ACPL-M72T (V) Typical Propagation Delay vs Input Forward Current 9

10 Test Circuit Diagrams ACPL-M7T High Speed Mode: Cin=pF R=9±% Vin=. -. V GND ACPL-M7T Vdd= V. µf C L=pF OUTPUT Vo V in V O V in 2.8 V V in 2 8% V dd V OL V dd Figure. High Speed Mode Test Circuit and Typical Waveform t PHL t PLH Cin=pF ACPL-M7T Vdd= V R=9±% Vin=. -. V. µf C L=pF OUTPUT Vo V CM V V V O SWITCH AT A: I F = ma V CM (PEAK) V dd- CM H + High Voltage Pulse V CM = V Figure 2. High Speed Mode CMH Test Circuit and Typical Waveform Cin=pF ACPL-M7T Vdd= V R=9±% Vin=. -. V. µf C L=pF OUTPUT Vo V CM V V O SWITCH AT A: I F = ma V CM (PEAK) V CM L + High Voltage Pulse V CM = V Figure. High Speed Mode CML Test Circuit and Typical Waveform

11 ACPL-M72T Low Power Mode: Vdd= V ACPL-M72T V in PULSE GEN.. µf V O C L =pf OUTPUT Vo INPUT Rin=7 GND V in 2 t PHL.8 V V in 2 t PLH 8% V dd V OL V dd Figure. Low Power Mode Switching Test Circuit and Typical Waveform ACPL-M72T Vdd= V R= R2=. µf C L=pF OUTPUT Vo + High Voltage Pulse V CM = V Figure. Low Power Mode High CMR, CMH Test Circuit ACPL-M72T Vdd= V R= Vin =. -.V R2=. µf C L =pf OUTPUT Vo + High Voltage Pulse V CM = V Figure. Low Power Mode High CMR, CML Test Circuit

12 Application Circuits Vin LOGIC I/O Ro Cin Vdd Truth Table R LIMIT Vout Vin LED Vout. µf L ON L H OFF H GND Figure 7. Recommended Application Circuit for ACPL-M7T High Speed Performance Vin LOGIC I/O Ro ½R LIMIT Vdd Truth Table Vout Vin LED Vout ½R LIMIT. µf L ON L H OFF H GND Figure 8. Recommended Application Circuit for ACPL-M72T Low Power Performance For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, the A logo and R 2 Coupler are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2-2 Avago Technologies. All rights reserved. AV2-28EN - June, 2