Intel 915G/915GV/910GL Express Chipset Memory Configuration Guide

Transcription

1 ntel 95G/95GV/9GL emory Configuration Guide White Paper September 24 ocument Number: 367-3

2 NFORATON N THS OCUENT S PROVE N CONNECTON WTH NTEL PROUCTS. NO LCENSE, EXPRESS OR PLE, BY ESTOPPEL OR OTHERWSE, TO ANY NTELLECTUAL PROPERTY RGHTS S GRANTE BY THS OCUENT. EXCEPT AS PROVE N NTEL S TERS AN CONTONS OF SALE FOR SUCH PROUCTS, NTEL ASSUES NO LABLTY WHATSOEVER, AN NTEL SCLAS ANY EXPRESS OR PLE WARRANTY, RELATNG TO SALE AN/OR USE OF NTEL PROUCTS NCLUNG LABLTY OR WARRANTES RELATNG TO FTNESS FOR A PARTCULAR PURPOSE, ERCHANTABLTY, OR NFRNGEENT OF ANY PATENT, COPYRGHT OR OTHER NTELLECTUAL PROPERTY RGHT. ntel products are not intended for use in medical, life saving, or life sustaining applications. ntel may make changes to specifications and product descriptions at any time, without notice. esigners must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." ntel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The ntel 95G/95GV/9GL chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local ntel sales office or your distributor to obtain the latest specifications and before placing your product order. ntel, Pentium and the ntel logo are trademarks or registered trademarks of ntel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 24, ntel Corporation 2 White Paper

3 Contents Overview emory Technology Supported llegal Configurations Valid Front Side Bus and emory Speeds ECC Support ntel 95G/95GV/9GL emory Organization and Operating odes7 Figures 2. Single-Channel ual-channel Asymmetric ual-channel Symmetric ixed RA emory Speeds... Figure. Single-Channel emory ode... 7 Figure 2. ual-channel Asymmetric emory ode... 8 Figure 3. ual-channel Symmetric emory ode... 9 Figure 4. System emory ode Styles... 9 Tables Table. emory Technology Support... 5 Table 2. Valid emory Configurations... 6 White Paper 3

4 Revision History Revision Number escription Revision ate - nitial Release. June 24-2 Updated to include ntel 95GV chipset August 24-3 Updated to include ntel 9GL chipset September 24 4 White Paper

5 Overview The ntel 95G/95GV/9GL chipset Graphics emory Controller Hub (GCH) is ntel s first dual-channel R/R2 emory Controller Hub with ntel Flex emory Technology. ntel has enhanced its memory architecture design to allow for maximum configuration flexibility while providing optimal performance when combined with R2-533 and an ntel Pentium 4 processor in the Land Grid Array 775 (LGA775) package with 8 Hz front side bus. This document details the 95G/95GV/9GL chipset GCH memory configurations and organization. t is intended for a technical audience interested in learning about the simplified population rules introduced by ntel Flex emory Technology and the 95G/95GV/9GL chipset GCH platform. This white paper will provide a brief background regarding the supported memory technologies and configurations, and then discuss the styles of memory organization and modes of operation.. emory Technology Supported The 95G/95GV/9GL chipset GCH supports either R or R2 memory technologies in the following configurations R-333 (PC27), R-4 (PC32) R2-4 (PC32), R2-533 (PC43) Table. emory Technology Support RA Technology Smallest ncrements (One SS ) Largest ncrements (One S ) aximum Capacity (Four S s) 256 b 28 B 52 B 248 B 52 b 256 B 24 B 496 B Gb 52 B 2 B 8 B (Note ) NOTES: This exceeds a 32-bit address limit of 4 GB. n a 32-bit system, only the first 4 GB of memory will be accessible..2 llegal Configurations The following configurations are not valid with the 95G/95GV/9GL chipset GCH: 64-b and 28-b emory Technology for R and R2 2-Gb and 4-Gb emory Technology for R2 x4, x32 S ouble-sided x6 S Registered S White Paper 5

6 No mixing of R and R2 S.3 Valid Front Side Bus and emory Speeds Table 2. Valid emory Configurations FSB RA ata Rate RA Type Single Channel Peak Bandwidth ual Channel Peak Bandwidth 533 Hz 333 T/s R-RA 2.7 GB/s 5.4 GB/s 533 Hz 4 T/s R-RA 3.2 GB/s 6.4 GB/s 8 Hz 4 T/s R-RA 3.2 GB/s 6.4 GB/s 8 Hz 4 T/s R2 - RA 3.2 GB/s 6.4 GB/s 8 Hz 533 T/s R2 - RA 4.25 GB/s 8.5 GB/s.4 ECC Support The ntel 95G/95GV/9GL chipset GCH does not support single-bit Error Correcting Code (or Error Checking and Correcting) on the R or R2 main memory interface. t will always operate in non-ecc mode with non-ecc and ECC R and R2 s. 6 White Paper

7 2 ntel 95G/95GV/9GL emory Organization and Operating odes The ntel 95G/95GV/9GL chipset GCH memory interface is designed with Flex emory Technology where it can be configured to support single-channel or dual-channel memory configurations and two modes of operation (R and R2). epending upon how the s are populated on each system memory channel, a number of different configurations can exist for R and R2: Single-Channel only one channel of memory is routed and populated, or if two-channels of memory are routed, but only one channel is populated; can be either channel A or channel B. ual-channel Asymmetric both channels are populated, but each channel has a different amount (B) of total memory. ual-channel Symmetric both channels are populated where each channel has the same amount (B) of total memory. The following sections explain and show the different memory configurations that are supported by the 95G/95GV/9GL chipset. 2. Single-Channel The system will enter single-channel mode when only one channel of memory is routed on the motherboard, or if two-channels of memory are routed, but only one channel is populated. n this configuration, all memory cycles are directed to a single channel. Figure. Single-Channel emory ode ntel 95G GCH 52 B B 52 B GCH 52 B B 52 B B GCH B B B 52 B B B B 52 B White Paper 7

8 2.2 ual-channel Asymmetric This mode is entered when both memory channels are routed and populated with different amounts (B) of total memory. This configuration allows addresses to be accessed in series across the channels starting in channel A until the end of its highest rank, then continue from the bottom of channel B to the top of the rank. Real world applications are unlikely to make requests that alternate between addresses that sit on opposite channels with this memory organization, so in most cases, bandwidth will be limited to that of a single channel. Figure 2. ual-channel Asymmetric emory ode ntel GCH 52 B B 52 B 256 B GCH 52 B 52 B GB 52 B B 256 B B 52 B 2.3 ual-channel Symmetric This mode allows the end user to achieve maximum performance on real applications by utilizing the full 64-bit dual-channel memory interface in parallel across the channels with the aid of ntel Flex emory Technology. The key advantage this technology brings is that the end user is only required to populate both channels with the same amount (B) of total memory to achieve this mode. The RA component technology, device width, device ranks, and page size may vary from one channel to another. Addresses are ping-ponged between the channels, and the switch happens after each cache line (64 byte boundary). f two consecutive cache lines are requested, both may be retrieved simultaneously, since they are guaranteed to be on opposite channels. 8 White Paper

9 Figure 3. ual-channel Symmetric emory ode ntel GCH 52 B B 52 B 52 B GCH 256 B 256 B 52 B 52 B B 52 B B 52 B Figure 4. System emory ode Styles White Paper 9

10 2.4 ixed RA emory Speeds The 95G/95GV/9GL chipset GCH will accept mixed R or R2 speed populations, assuming the SP on the S are programmed with the correct information and the BOS is programmed as outlined in ntel s BOS reference code. n all operating modes (Single-Channel, ual Channel Asymmetric, and ual-channel Symmetric) the frequency of the System emory will be set to the lowest frequency of all s populated in the system, as determined through the SP registers on the s. For example, a R2-533 installed with a R2-4 should run at 4 Hz. The R2-533 should downshift to R2-4 timings, thus allowing the system to run at 4 Hz speeds. The R2-533 will only downshift to R2-4, if the timings for R2-4 are programmed in the R2-533 s SP. White Paper