Michael David Bryant 1 11/1/07
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1 Michael David Bryant 1 11/1/07 Basic electronics Operational Amplifiers (OpAmps) OpAmp Features Other OpAmp Specifications & Issues Amplifier Configurations Inverting amplifier Multiple Inputs: Sum Over Inverting Point Three esistor Equivalent Feedback Network Noninverting Amplifier Differential Amplifier Instrumentation Amplifier Design Guidelines Passive Element Filters Basic OpAmp Active Filters Digital to Analog Converters (D/A) D/A: Weighted Current Sources D/A: 2 Ladder Network Sample and Hold Circuits Analog to Digital Converters (A/D) A/D Successive Approximation A/D Parallel (flash) converters Hybrid Digital/Analog Systems
2 Michael David Bryant 2 11/1/07 Purpose Amplify (boost) weak signal emove noise or other unwanted signal components filtering common mode rejection Preprocess signal for later operations Attenuate high frequencies: antialiasing before A/D conversion
3 Michael David Bryant 3 11/1/07 Basic electronics Operational Amplifiers (OpAmps) V, V usually between 0 and 25 volts
4 Michael David Bryant 4 11/1/07 OpAmp Features 1. Very high gain eo / ei = A 10 6 to Large bandwidth (MHz or more) 3. High input impedance i 100 kω to 100 MΩ ( small input load currents) 4. Low output impedance o 10 1 to 10 2 Ω 5. Differential inputs ei = ea eb 6. High Common Mode ejection atio (CM) 50 to 100 db. (db = 20 log10 ) CM: same common mode signal e CM into ea & eb tiny eo If channel a & b input impedances same, minimizes effect of signals induced on both channels (e.g. 60 Hz from building supply). Common Mode Gain: CMG = A/CM ( e.g., = 10 6 / ). 7. Temperature dependent parameters: design to minimize effects. 8. Voltage Supply ejection atio (VS) gauges effect of power supply drift & variations V and V as equivalent input ei. 9. Input Offset voltage Voffset : Manufacturing imperfections & temperature variations eo 0 when ei = 0 (violating desired eo = A ei ). To correct, adjust Voffset :
5 Michael David Bryant 5 11/1/07 V e o V offset V (or V ) Voffset allows low cost OpAmp. Imperfections corrected (cheaply) at installation, not (expensively) during chip manufacture. 10. OpAmp acts as controllable valve. V Output V eo V A e i V A. 11. Input bias currents I and I (10 na to µa) flow through (b) and (a) input terminals to bias input transistors (FET gate or BJT base). Voltage drop developed across input elements must be balanced (same at both terminals) so that eo = 0. Balanced input resistances to and. 12. Input offset currents I and I residual eo 0 unless minimized with potentiometer on one input to fine tune. Can also adjust Voffset. Puts upper limit on values of input resistors (minimize voltage drops due to I and I ).
6 Michael David Bryant 6 11/1/ Class B operation often used in output stage: complementary npn & pnp in push/pull (Nearly identical amplifier circuitsstage 1 & stage 2 arranged in parallel. Stage 1 amplifies only positive voltages, and switches off for negative. Stage 2 amplifies only negative, and switches off for positive.) Crossover distortions possible (small signals) in dead space as transistors in stages switch on/off. e o stage 1: positive response stage 2: negative response e i dead space: transistors on/off
7 Michael David Bryant 7 11/1/07 Other OpAmp Specifications & Issues A. Slew rate S de o dt max important to avoid large signal distortions. ei = E sin ωt ; S = E ω cos ωt = E ω max equire S 2π f E for amp to follow largest voltage swing. B. Compensation: Lead/lag network to control phase margin when negative feedback. For stable amplifier design gain ( 2 1 for inverting amplifier, 1 2 for noninverting 1 amplifier), require closed loop response curve to meet open loop curve where slope of closed loop curve is 20 db/dec. 20dB/dec 1 st order term 90 phase limited signal growth (phase margin = = 90 stable closed loop system) Internally compensated: manufacturer provides network for 20 db/decade; limits bandwidth but unconditionally stable. Externally compensated: Install capacitance ( pf) across indicated frequency compensation terminals to control bandwidth and closed loop gain (40 db 20dB). Manufacturer specifies needed capacitance. Conditionally stable (for given closed loop gain). M db open loop: gain A 20 db/dec design gain: closed loop 20 db/dec 40 db/dec 20 db/dec externally compensated: stable design (crosses 20 db/dec) uncompensated: unstable design (closed loop design crosses 60 db/dec) internally compensated: unconditionally stable (20 db/dec up to 100kHz) 0 open loop at 20 db/dec meets closed loop gain 60 db/dec 1k 1 M f (Hz)
8 Michael David Bryant 8 11/1/07 Unstable Feedback Oscillation: Sinusoid grows output sine: G causes phase lag input sine G H additional phase lag of H inverts sine First cycle: No feedback, but GH inverts. First cycle: Negative feedback & GH inversion ( 360 phase) add constructively with input. G H After second pass, feedback promotes signal growth. Further passes unstable!
9 Michael David Bryant 9 11/1/07 C. Power Supply Filter Capacitors (10 1 to 1 µf) to minimize power supply fluctuations V 0.1 µf V 0.1 µf
10 Michael David Bryant 10 11/1/07 Amplifier Configurations Inverting amplifier 1 i 2 i 1 e a 2 e s e b e o i 3 3 a. DC analysis DC biases: Very large i e DC ab 0 edc a edc b Small bias current i DC 3 0 edc b = idc e DC a 0 : node a at virtual ground! Negative feedback (via 2 ) enhances.
11 Michael David Bryant 11 11/1/ b. 3 = 1 2 = 1 2 current voltage drop: to balance input bias If 3 = 0, e DC a edc b = 0 idc 1 = 0 & idc 2 = edc o edc a 2 e DC o = idc equired: zero input es = 0 eo = e DC o eac o = 0. Achieved via 3 = 1 2 DC DC DC (balanced bias currents i 3 = i 1 i 2 ). c. AC signal analysis Currents into inverting terminal negligible (very large i ) i1 i2 e s ea = e o ea, 1 2 with eo = A ei = A ( ea eb )= A ea eo es = A 1 1/2 (1 A) 2 /1 at low freq, A >> 1 breaks down at high freq, A = A(f) & i = i(f) d. Input resistance in = e s i1 = frequency es 1 es ea 1 at low e. Output resistance out o ( 1 1/2 ) A (10 1 to 10 0 ) small
12 Michael David Bryant 12 11/1/07 Multiple Inputs: Sum Over Inverting Point e 1 e 2 e 3 i i 2 i 3 e a e b 2 e o 3 eo 2 { e 1 11 e 2 12 e 3 13 } 3 =( ) 2
13 Michael David Bryant 13 11/1/07 Three esistor Equivalent Feedback Network 2a 2b 2c 1 i e a e s e b e o 3 Equivalent feedback resistor 2 = 2a 2b 2a 2b /2c Small 2c large equivalent 2 without big (noisy) resistors For higher gain Opamp designs
14 Michael David Bryant 14 11/1/07 Noninverting Amplifier e o e s 3 = 1 2 a. Input on noninverting terminal, feedback to inverting terminal for stability b. eo es = A 1 A 1/(1 2 ) 1 2 low freq, A >> 1 c. Input resistance in extremely large i A 1 2/1 >> i d. Output resistance out same as inverting amp.
15 Michael David Bryant 15 11/1/07 Differential Amplifier 1 2 e s1 3 e o e s2 4 a. Common mode rejected (e.g., drift) via high CM b. eo ( ) e s2 3 = e s1 = 2 1 ( e s2 es1 ) 4 = 2 c. īn = 1 (small) in 3 4 (small)
16 Michael David Bryant 16 11/1/07 Instrumentation Amplifier e s1 1 2 e o 3 4 e s2 Combine advantages: High input impedance / noninverting terminals Differential stage (CM)
17 Michael David Bryant 17 11/1/07 Design Guidelines A. OpAmp selection Gain & bandwidth within scope of amp design Peak to Peak output voltage swing within range of supply rails (V, V ) Slew rate S dv dt max Acceptable noise figure (NF) over operating range B. Stability frequency compensation (internal or external) for 20 db/dec external: resisitors and capacitors specified by manufacturer 20 db/dec. at desired gain stable amplifier C. Power supply Supply rails V, V sufficient for swings minimize power supply fluctuations with filter capacitors avoid draining: power peaks sufficient V, V not too high: excessive shot noise
18 Michael David Bryant 18 11/1/07 D. esistor selection in = 1 min < 1 < max min lower bound from signal source (i, v) impedance: want high max limited by offset current ( DC drop at output) & thermal noise V oc a = [{ 1 2 } ioc ] max < 10% max allowed distort; oc: offset current 2 /1 gain for inverting amp, 1 2 /1 for noninverting amp 3 = 1 2 Networks (manufacturer) voltage offset compensation E. Offset ( defined by ei = 0 eo 0 ) V oc a << V offset Voffset reduced via voltage offset temperature dependence within operating range zero at Toperating δvout for δt < allowable distortion F. Distortion components (total < allowable) common mode / bias current (CM) V oc δvout power supply fluctuations (VS) insufficient bandwidth, slew rate, supply rails
19 Michael David Bryant 19 11/1/07 Passive Element Filters T network π network Z1/2 Z1/2 Z1 Z2 Zload 2 Z2 2 Z2 Zload.. Goal: overall impedance = Zload Capacitor: C, Inductor: L, low cutoff frequency: fl, high cutoff frequency: fh Designs: Low pass: Z1 = L, Z2 = C, fl = 0, fh = High pass: Z1 = C, Z2 = L, fl = 1! LC 1 4! LC, f h = Bandpass: Z1 = L1 series C1, Z2 = L2 C2, fl, fh depend on Z load Bandreject: Z1 = L1 C1, Z2 = L2 series C2, fl, fh depend on Z load
20 Michael David Bryant 20 11/1/07 Basic OpAmp Active Filters 1st order active filter C 1 2 e s 3 e o Inverting amp with feedback C & 2 : H(s) = e o(s) es(s) 2 1/sC = 1 low frequency gain: db cutoff frequency: fc = 2/1 2 C s 1 1 2π 2 C
21 Michael David Bryant 21 11/1/07 2nd order active filter, Low gain type 1 2 C 1 e s C 2 a b e o Noninverting amp with coupling capacitors. Low frequency gain: K = 1 b a H(s)= e o(s) es(s) K = s 2 12C1C2 s [2 C1 1C1 (1 K) 1C2] 1 cutoff (natural) frequency: fc = 2π 1 12 C1 C2
22 Michael David Bryant 22 11/1/07 2nd order active filter, High gain type 4 C e s C 1 3 e o Inverting amp with feedback C2 (4 2 ), input 1 2, coupling capacitor C1 H(s) = e o(s) es(s) 1/12C1C2 = s 2 s [1/1 1/4 1/2](1/C1) 1/42C1C2 cutoff (natural) frequency: fc = 2π 1 42 C1 C2 Higher order filters usually cascade 1st & 2nd order filters
23 Michael David Bryant 23 11/1/07 Analog Integrator Inverting amp with feedback C & input eplace feedback with impedance 1/sC: H(s) = e o(s) e I (s) = "1/sC = " 1 sc Integrator: e o (t) = " 1 C # e o (t)dt
24 Michael David Bryant 24 11/1/07 2 esistance Ladder Enables digital (software) control of resistance Input resistance can be changed insitu V i Z V o operation switches control currents to terminals: noninverting (ground) inverting terminals (virtual ground) total ladder current constant currents half (left to right), each ladder step resistance into opamp looking into any node: 2 2 currents split in half
25 Michael David Bryant 25 11/1/07 Digital to Analog Converters (D/A or DAC) Converts digital (binary number) to analog voltage Settling time ts : time required for analog input (voltage or current) to settle within ± LSB/2 following input code change typical: nsec to 100 µsec circuits downstream add dynamics increases ts
26 Michael David Bryant 26 11/1/07 D/A: Weighted Current Sources 1, Sk closed { Switch function ak = controlled by bit settings 0, Sk open "Bit" currents ik sum, give output: 3 Vo = Vs 2 ak/1k k=0 Problems: Many bits many resistors Usually 1k = 2 k for binary powers requires accurate resistors: each resistor must be precisely 1/2 its neighbor
27 Michael David Bryant 27 11/1/07 DAC: 2 Ladder Network 2 Ladder Network DACs in 8, 10, 12, 14, 16, or 18 bits Output Vo more accurate: only 2 resistor values needed similar to weighted current source: currents in powers of 2 noninverting terminal at ground, inverting terminal at virtual ground ladder currents constant, independent of switches Example: 4 bit D/A (Bits 3,2, 1, 0) 2 i0 =V0 =2 it i0 = it 2 i1 =V1 =( i0 it )V0 i1 = 2 i0 2 i2 =V2 =( i1 i0 it )V1 i2 = 2 i1 3 i = ak ik ; k=0 3 Vo = ak V k = 2 ak ik = 2 i k=0 k=0
28 Michael David Bryant 28 11/1/07 Sample and Hold Circuits Analog input voltage V MOS enhancement FET S control signal G D voltage follower ( = 0) 2 i D comparator C 5 V buffered output (same V but larger i) V o from CPU via control register high: sample low: hold V In higher performance A/D converters Operation (Sample & Hold Input during A/D conversion) switch (FET) closes & analog voltage charges capacitor capacitor voltage to OpAmp constant (held) after switch opens MOSFET: Positive gate voltage attracts electrons (charge carriers) into channel, increasing conductance FET "switch" characteristics V GS low 10 MΩ (open switch) V GS high 200 Ω (closed switch) i D(mA) ! = 2V/10 ma 7V 5V V = 4V GS V = 0V GS 5 10 V (V) DS 10 M!
29 Michael David Bryant 29 11/1/07 Comparator: Special OpAmp circuit prone to saturation, but optimized for fast recovery from saturation V (high), V1 > V2 Vout = { V (low), V1 < V2 V 1 V 2 comparator output voltage
30 Michael David Bryant 30 11/1/07 Analog to Digital Converters (A/D or ADC) Convert analog voltage to digital (binary) 1) A/D Successive Approximation 4 bit D/A I test a b V / in V in analog input from sample & hold comparator B 3 B 2 B 1 B 0 I MSB voltage limiting diode pair I a b LSB clock start D a b V d control logic Input frozen by sample & hold Diodes limit Vd swing due to I = V in I test series of n (# bits) bit tests places input in bin (voltage range) D/A converter generates test currents I test (or voltages), to be compared to input final D/A number = A/D result I test reflects current D/A setting I = V in I test Vd high or low logic
31 Michael David Bryant 31 11/1/07 Test sequence, 4 bit A/D 4 tests test bit tested D/A test setting bit test result 1 3 (MSB) 0111 a3 2 2 a3 011 a2 3 1 a3 a2 01 a1 4 0 (LSB) a3 a2 a1 0 a0 ak = { 1, Vd > 0 I test < Vin / 0, Vd < 0 I test > Vin / Bit test result ak causes D/A to output current I test that CANCELS a component of input current Vin /, thereby fine tuning D/A register. Final result a3 a2 a1 a0. Problem: accurate but moderate speed. Conversion times 1 µs to 100 µs.
32 Michael David Bryant 32 11/1/07 Capacitor Based Successive Approximation Charge all capacitors to V in o lower plate = input voltage V in o upper plate = ground For ADC, Switch o leftmost C (MSB) to V ref o other C s to V ref o ground switch open Comparator determines if
33 Michael David Bryant 33 11/1/07 A/D Parallel Flash ADC converters V in V ref 2/3 V ref decoding logic ( 1 level) MSB LSB 1/3 V ref latch (switches on) Speeds exceed 500 MHz: up to 4 GHz for 4 bit converter Voltage dividing resistors create 2 n voltage levels or bins Comparators which "bin" contains input Big Problem: need (2 n 1) resistors & comparators for 2 n bins requires large silicon area on chip usually limited to 3 to 6 bits Other problems: parasitic capacitance at each resistor limits bandwidth many resistors increase power consumption
34 Michael David Bryant 34 11/1/07 Pipelining Sample & Hold (S/H) Multiple conversion stages 1 or 2 bit each stage o Flash converters do ADC o DAC converts bits to voltage o Subtract bit voltage from input, create residue o Amplify residue o Next stage does next bits o Order: MSB to LSB Pipeline: Samples flow through, 1 stage at a time Advantages N to 2N COMPAATOS High sampling frequency, with > 8 bits Drawbacks Complexity Power consumption
35 Michael David Bryant 35 11/1/07 Sigma Delta ΣΔ (Delta Sigma ΔΣ) Converters For low frequency signals Output: pulses of constant amplitude & duration Interval between pulses proportional to input voltage. Higher input 1 Greater slope of integrator output (~ramp) More frequent comparator triggers & Shorter intervals between Count pulses: count ~ input voltage
36 Michael David Bryant 36 11/1/07 Hybrid Digital/Analog Systems Noise perspective: analog & digital systems incompatible analog contaminated by digital pulses AC noise via power supply feedback stray C 's ground loops digital contamination analog lower frequency filtering reduced digital pulses Prescription: Isolate systems 1. Separate analog & digital grounds 2. Connect digital & analog at ONE point ONLY (avoid ground loops) 3. Provide separate analog & digital supply voltages 4. Electrostatic shielding (Faraday cage) around analog circuit. Connect one end only to analog ground 5. At especially sensitive interconnections, consider electrooptic coupling 6. Consider using emitter coupled logic (ECL) in digital section for less spurious signal generation 7. If analog & digital on same IC, separate with wells (pn junctions)
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