Lab 2 op-amp Circuits. Experiment 2.1 Basic op-amp circuits Experiment 2.2 Non-linear op-amp circuits. Basic op-amp circuits

Transcription

1 Lab 2 op-amp Circuits Experiment 2. Basic op-amp circuits Experiment 2.2 Non-linear op-amp circuits 02.. Objective Basic op-amp circuits. To sketch the ollowing basic op-amp circuits and explain the operation o each: (a) Inverting ampliier (b) Non-inverting ampliier (c) Voltage ollower (d) Dierential ampliier (e) Summing ampliier () Integrator and dierentiator. 2. To analyze and design circuits o the type listed in item I above or input & output impedances, voltage gain and bandwidth. 3. To trouble shoot and analyze aults in the op-amp circuits Hardware required a. Power supply variable regulated low voltage dc source b. Equipments AFO, CO, DMM c. esistors - d. Capacitors - e. Semiconductors - IC 74 op-amp. Miscellaneous - Bread board and wires 2..3 Pre Lab questions ) Identiy each o the op-amp conigurations 2) A nn-inverting ampliier has o K o 00K. Determine V and (Feedback voltage and eedback raction), i Vo = 5V 3) For the ampliier in Fig. (b) Determine the ollowing (a) A CL (NI) (b) Vo (c) V 4) Find the value o F that will produce closed-loop gain o 300 in each ampliier in ig(c)

2 5) Determine the approximate values or each o the ollowing quantities in Fig (d). 6) I a signal voltage o 0mV rms is applied to each ampliier in Fig(e), What are the o/p voltage? 7) Determine the input and output impedances or each ampliier coniguration, (Zin=0M, Zo=75, AOL = 75,000). in ig() 8) Determine the BW o each o the ampliiers in Fig. The op-amps have an open-loop gain o 90dB and a unity gain bound width o 2MHz. 9) Determine the o/p voltage o each ampliier in Fig (h).

3 2..4 Theory In this laboratory experiment, you will learn several basic ways in which an op-amp can be connected using ve eedback to stabilize the gain and increase the requency response. The extremely high open-loop gain o an op-amp creates an unstable situation because a small noise voltage on the input can be ampliied to a point where the ampliier in driven out o its linear region. Also unwanted oscillations can occur. In addition, the open-loop gain parameter o an op-amp can vary greatly rom one device to the next. Negative eedback takes a portion o o/p and applies it back out o phase with the input, creating an eective reduction in gain. This closed-loop gain is usually much less than the open-loop gain and independent o it Closed loop voltage gain, A CL The closed-loop voltage gain is the voltage gain o an op-amp with external eedback. The ampliier coniguration consists o the op-amp and an external ve eedback circuit that connects the o/p to the inverting input. The closed loop voltage gain is determined by the external component values and can be precisely controlled by them Non-inverting ampliier An op-amp connected in a closed-loop coniguration as a non-inverting ampliier with a controlled amount o voltage gain is shown in Fig 3--. The input signal is applied to the non-inverting (+) input The output is applied back to the inverting (-) input through the eedback circuit (closed loop) ormed by the input resistor and the eedback resistor. This creates ve eedback as ollows. esistors and orm a voltage-divider circuit, which reduces Vo and connects the reduced voltage V to the inverting input. The eedback is expressed as V ( ) Vo The dierence o the input voltage, V in and the eedback voltage, V is the dierential input o the opamp. This dierential voltage ins ampliied by the gain o the op-amp and produces an o/p voltage expressed as Vo Vin The closed-loop gain o the non-inverting ampliier is, thus A CL(NI) =

4 Notice that the closed loop gain is * independent o open-loop gain o op-amp * set by selecting values o I and An expression or the input impedance o a non-inverting ampliier can be written as Where Zin(NI) = ( A OL ) Z IN A OL = open-loop voltage gain o op-amp Z IN = internal i/p impedance o op-amp (without eedback) = attenuation o the eedback circuit V = Vo Eq. (-2-3) shows that the input impedance o the non-inverting ampliier coniguration with ve eedback is much greater than the internal o/p impedance o the op-amp itsel. The o/p impedance o a NI ampliier can be written as Zo Z o ( NI ) A OL This eq. shows that the o/p impedance o NI ampliier is much less than the internal o/p impedance, Zo o the op-amp Voltage ollower The voltage ollower coniguration is a special case o the non-inverting ampliier where all the o/p voltage is eedback to the inverting input by straight connection, as shown in ig As you can see, the straight eedback connection has a voltage gain o (which means there is no gain). A CL (VF) = The most important eatures o the voltage ollower coniguration are its very high input impedance and its very low output impedance. These eatures make it a nearly ideal buer ampliier or interacing high-impedance sources and low-impedance loads. Z A ) Z IN ( VF ) ( ol IN Z O( VF ) ZO A OL

5 As you can see, the voltage ollower input impedance is greater or a given AOL and ZIN than or the non-inverting ampliier. Also, its o/p impedance is much smaller Inverting ampliier An op-amp connected as an inverting ampliier with a controlled amount o voltage gain is shown in ig The i/p signal is applied through a series i/p resistor to the inverting input. Also, the o/p is ed back through to the same input. The non-inverting i/p is grounded. An expression or the o/p voltage o the inverting ampliier is written as Vo VIN The ve sign indicates inversion. The closed-loop gain o the inverting ampliier is, thus ACL( I ) The i/p & o/p impedances o an inverting ampliier are Zin(I) = i Zo Zo(I) = A OL The o/p impedance o both the non-inverting and inverting ampliier conigurations is very low; in act, it is almost zero in practical cases. Because o this near zero output impedance, any load impedance connected to the op-amp o/p can vary greatly and not change the o/p voltage at all Summing amplier The summing ampliier is an application o the inverting op-amp coniguration. The summing ampliier has two or more inputs, and its output age is proportional to the algebraic sum o its input voltages. Fig shows a two-input inverting summing ampliier. Case-:I all the three resistors are equal ( = 2 = =) then Vo = - (V inl + V INZ ) The above equation shows that the o/p voltage has the same magnitude as the sum o two input voltages but with a ve sign indicating inversion.

6 Case-2: when is larger than the input resistors, the ampliier has a gain o value o each equal value input resistor (=2=). the general expression, where is the or the o/p is Vo ( V ) in Vin2 The above equation shows that the o/p voltage has the same magnitude as the sum o all the input voltages multiplied by a constant determined by the ration -. Case-3: By setting the ration / equal to the reciprocal o the number o inputs (n), ie., = summing ampliier can be made to produce the mathematical average o the input voltages. n, a Case-4: A dierent weight can be assigned to each input o a summing ampliier by simply adjusting the values o the input resistors. In this case, the o/p voltage can be expressed as Vo ( Vin Vin 2 2 The weight o a particular input is set by the ration o to the resistance x or the input (x,, 2,.) Subtractor or Dierential ampliier The unction o a subtractor is to provide an o/p proportional to or equal to the dierence o two input signals. A basic dierential ampliier or a subtractor circuit is shown in ig The o/p voltage o the dierential ampliier can be expressed as Vo ( V ) V2 Thus it can be seen that the o/p voltage depends on the dierence o the input voltages. (V-V2) can be suitably ampliied choosing the values o /. The circuit also behaves as a subtractor i =.

7 Integrator An op-amp integrator simulates mathematical integration which is basically a summing process that determines the total area under the curve o a unction ie., the integrator does integration o the input voltage waveorm. Here the input element is resistor and the eedback element is capacitor as shown in ig The o/p voltage is given by t Vo Vsdt Vc( t 0) c o Where Vc (t=0) is the initial voltage on the capacitor. For proper integration, c has to be much greater than the time period o the input signal. It can be seen that the gain o the integrator decreases with the increasing requency so, the integrator circuit does not have any high requency problem unlike a dierentiator circuit. However, at low requencies such as at dc, the gain becomes ininite. Hence the op-amp saturates (ie., the capacitor is ully charged and it behaves like an open circuit). In order to limit the gain o the integrator at low requencies, usually the eedback capacitor is shunted by a resistance, and hence saturation problems can be avoided. A practical integrator circuit is shown in Fig Dierentiator An op-amp dierentiator simulates mathematical dierentiation, which is a process o determining the instantaneous rate o change o a unction. Dierentiator perorms the reverse o integration unction. The o/p waveorm is derivative o the i/p waveorm. Here, the input element is a capacitor and the eedback element is a resistor. An ideal dierentiation is shown in ig

8 The o/p voltage is given by dvs Vo c( ) dt For proper dierentiation, c has to be much smaller than the time period o the input signal. It can be seen that at high requencies a dierentiator may become unstable and break into oscillation. Also, the input impedance o the dierentiator decreases with increase in requency, thereby making the circuit sensitive to high requency noise. So, in order to limit the gain o the dierentiator at high requencies, the input capacitor is connected in series with a resistance and hence autiding high requency noise and stability problems. A practical dierentiator circuit is shown in ig Troubleshooting As a technicial, you may encounter situations in which an op-amp or its associated circuitry has malunctioned. The op-amp is a complex IC with many types o internal ailures possible. However, since you cannot trouble shoot the op-amp internally, you can treal it as a single device with only a ew connections to it. I it ails, you replace it just as you would a resistor, capacitor, or transistor Faults in the non-inverting ampliier. The irst thing to do when you suspect a aulty circuit is to check or the proper supply voltage and ground. Having done that, several other possible aults are as ollows. Open eedback resistor: I the eedback resistor, in Fig. 3-- opens, the op-amp is operating with its very high open-loop gain, which causes the input signal to drive the device into non-linear operation and result in a severely clipped o/p signal. Open input resistor: In this case, you still have a closed-loop coniguration, But, since is open and eectively equal to, the closed-loop gain rom equation -2-2 is ACL ( NI ) 0 This shows that the ampliier acts a voltage ollower. You would observe an o/p signal that is same as the input. Internally open non-inverting input: In this situation, because the input voltage is not applied to the opamp the o/p is uro.

9 Other op-amp aults: In general, an internal ailure will result in a loss or distortion o the o/p signal. The best approach is to irst make sure that there are no external ailures or aulty conditions. I everything else is good, then the op-amp must be bad Faults in the voltage ollower The voltage ollower is a special case o the non-inverting ampliier. Except or a bad op-amp, a bad external connectietor a problem with the oset null potentiometer, about the only thing that can happen in a voltage ollower circuit is an eedback loop. This would have the same eect as an open eedback resistor, as previously discussed Faults in the inverting ampliier open eedback resistor: In ig. 2--3, i opens the i/p signal still eeds though the input resistor and is ampliied by the high open-loop gain o the op-amp. This orces the device to be driven into nonlinear operation. This is the same result as in the non-inverting ampliier coniguration. Open input resistor: This prevents the i/p signal rom getting to the op-amp i/p, so there will be no o/p signal. Failures in the op-amp itsel or the oset null potentiometer have the same eects as previously discussed or the non-inverting ampliier coniguration Faults in summing ampliiers I one o the input resistor in a unity-gain summing ampliier opens, the o/p will be less than the normal value by the amount o the voltage applied to the open input. Stated another way, the o/p will be the sum o the remaining input voltages. I the summing ampliier has a non-unity gain, on open input resistor causes the o/p to be less than normal by an amount equal to the gain times the voltage at the open input Experiment. Non-Inverting ampliier. Design a non-inverting ampliier or the gain o 5. Let =.5k Assemble the circuit..2 Feed sinusoidal input o amplitude 00mV and requency KHz.3 Observe the input voltages and o/p voltage on a CO. Tabulate the reading in Table Calculate closed-loop gain (A CL ), bandwidth (BW), gain-bandwidth product (GBW), input impedance (Zi), and output impedance (Zo). Tabulate the readings in Table Compare the experimental results with the theoretical values. 2. Voltage ollower 2. Assemble a voltage ollower circuit. 2.2 Feed sinusoidal input o amplitude 00mv and requency Khz. 2.3 Observe the input and output voltages on a CP. Tabulate the readings in Table Calculate A CL, Bw, GBW, Zi and Zo. Tabulate the readings in Table Compare the experimental results with the theoretical values. 3. Inverting ampliier 3. Design an inverting ampliier or the gain o 5. Let =.5k. Assemble the circuit. 3.2 Feed sinusoidal input o amplitude 00mv and requency KHz. 3.3 Observe the input and output voltages on a CO. Tabulate the readings in Table 2--.

10 3.4 Calculate A CL, Bw, GBW, Zi and Zo. Tabulate the readings in Table Compare the experimental results with the theoretical values. 4. Summing ampliier 4. Assemble an adder circuit with ==0k and 2=47k. 4.2 Feed sinusoidal input o amplitude 00mv and requency KHz to each input. 4.3 Observe the input voltages and output voltage on a CO Find the magnitude o the o/p voltage and tabulate the reading in Table Compare the experimental results with the theoretical values. 5. Dierential ampliier 5. Assemble a dierential ampliier circuit with ==0k 5.2 Feed V=00mv and V2=50mv sinusoidal signal o requency KHz. To get 2 signals rom the same source, use a high resistance potentiometer. 5.3 Observe the i/p and o/p voltages on a CO. Find the magnitude o the o/p voltage and tabulate the readings in Table Compare the experimental results with the theoretical value. 6. Integrator 6. Assemble an integrator circuit with =K and C=0.µ connect o value M across the capacitor. 6.2 Feed +IV, 500Hz square wave input. 6.3 Observe the input and output voltages on a CO. Determine the gain o the circuit and tabulate the readings in table 2--3.Model waveorm is shown in ig Plot the i/p and o/p voltages on the same scale on a linear graph sheet. 7. Dierentiator 7. Assemble a dierentiator circuit with =0K and C=0.05µ. Connect a resistor o value 470 between the source and the capacitor. 7.2 Feed + 0.V, 5 KHz triangular wave input. 7.3 Observe the input and output voltages on a CO. Determine the gain o the circuit and tabulate the readings in table Model waveorm is shown in ig Plot the i/p and o/p voltages on the same scale on a linear graph sheet Post Lab questions. What is the relationship, i any, between the polarity o the output and input voltages in your experimental op-amp? eer to your data. 2. Can the summer operated as a subtractor? Conirm your answer with the experimental data. 3. Look at Table 2-- and comment on the statement: The closed-loop gain-bandwidth product is a constant or a given op-amp. 4. Determine the bandwidth o a non-inverting ampliier, voltage ollower and inverting ampliier that were implemented in the laboratory. 5. Determine the gain-bandwidth product o each ampliier. 6. Determine the i/p and o/p impedances o each ampliier. 7. Determine the most likely aults or each o the ollowing symptoms in ig with a 00mv signal applied.

11 (a) No o/p signal (b) o/p severely clipped on both +ve & -ve swings. 8. Determine the eect on the o/p i the circuit in ig. has the ollowing ault (one at a time). (a) o/p pin is shorted to the inverting i/p (b) 3 is open (c) 3 is 0K instead o 90. (d) and 2 are swapped. 9. (a) What is the normal o/p voltage in ig. 2--4? (b) What is the o/p voltage o 2 opens? (c) What happens i 5 opens? 2..8 Advanced problems. Design a non-inverting ampliier with an appropriated closed-loop gain o 50 and a minimum i/p impedance o 00M. 2. Design an inverting ampliier using a 74 op-amp. The voltage gain must be 68 +5% and the input impedance must be approximately 0K. 3. Design a non-inverting ampliier with an upper critical requency o 0 KHz. 4. Design an inverting ampliier i a midrange voltage gain o 50 and a bandwidth o 20 KHz is required. 5. Design an integrator that will produce an o/p voltage with a slope o 00mv/µs when the i/p voltage is a constant 5v. Speciy the input requency o a square wave with an amplitude o 5v that will result in a 5v peak-to-peak triangular wave o/p. 6. Show the connection o 3-stage ampliiers using 74 op-amp with gains o +0, -8 and -27. Use a 270K eedback resistor or all three stages. What o/p voltage will result or an i/p o 50µv?